PMOS 3T resistor-biased cascoded current mirrors

Schematic Diagram

SPICE Simulations

Operating Point Analysis

Operating point DC measurement results (re-formatted for display):

n1 = 0.773
n2 = 0.650
n3 = 0.273
n4 = 0.771
vp = 1.3
v1#branch = 50 uA
v2#branch = -50.0 uA
(v2#branch/v1#branch) = 1.00

And our relevant transistors' device parameters at the DC OP (re-formatted for display):

device  m3          m2          m1                                                                  
model   pmos        pmos        pmos                                                                
gm      767.124 uS  445.368 uS  445.348 uS                                                              
rds     12.168 kR   896.15 kR   892.41 kR                                                               
id      50.0 uA     50.002 uA   50 uA                                                                   
vgs     0.498       0.527       0.527                                                                   
vds     0.121       0.529       0.527                                                                   
vth     0.440       0.337       0.337                                                                   
vdsat   0.111       0.198       0.198 

As seen given our close Vds for both source and mirror transistors, both branches are very well matched in performance.

DC Analysis (Sweep)

For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 1.3V to 0V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage.

Monte Carlo Analysis

In our Montecarlo analysis, we are measuring the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistor parameters when added together can affect the performance of the overall circuit (please refer to the NMOS counterpart article for additional setup details for this simulation).

Results

For the cascoded current mirror, we can make the following observations

• The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.111 + 0.198 >> 0.309

• However as shown with the current sizing, the mirror output can go up to maximum 0.8V (at least ~0.5 vload voltage relative to vp) to yield its maximum Rout. (seen from the plot above where the slope is linear).

• Error Measurement: We see a variation of 49.926uA to 50.009uA over a linear operating vload range of 0.5 to 1.3V. This is equivalent to an error of 83nA or 0.166% relative to our reference.

Figures of Merit

Output Resistance Rout: 9.639MΩ (measured from 0.5 to 1.3V linear range).

Compliance Voltage Vload min: ~0.5V (from VP)

References

• Designing Analog Chips (Hans Camenzind)

• • Chapter 3 (pages 3-7)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.