PMOS current mirror
Much like for the simple NMOS current mirror, the PMOS mirror is used alternatively when a mirrored current "source" (as opposed to a sink) is required for biasing a particular analog block.
We can compare the complementary mirror topologies in many ways by constraining design parameters e.g. size based on the bias (diode) device to match vbn/p bias conditions, or size based on the the mirror device to maintain rds, or size accordingly to maintain output load headroom. In our case here, since we are primarily interested in comparing the mirror output resistance under the same output load conditions: we have chosen to maintain the output load headroom and compare the output resistance.
To attain the same headroom for our load, we need to have the same minimum vdsat for the mirror device (we want roughly the same Veff overdrive). However due to the lower mobility at large lengths for PMOS devices, it is necessary to employ a larger W/L ratio by increasing the devices' widths significantly (as shown below).
For our reference, the nmos W/L ratio was 2.5, whereas the PMOS W/L ratio is 25: a factor of 10.
Results provided here help compare complementary topologies under similar min vdsat (load headroom conditions), simulation results are provided below.
* dev <nets> <values> * ---------------------------------------- V1 n_pos 0 1.3V I1 n1 0 50uA M1 n1 n1 n_pos n_pos pmos W=50u L=2u M2 n2 n1 n_pos n_pos pmos W=50u L=2u V2 n_pos n2 0.55957V
Walking through our simulation results we have:
Operating Point Analysis
Nominally with matched output load voltage (matched Vds across output transistor), calculating the operating point DC voltages and currents for our mirror.
Operating point DC measurement results (re-formatted for display):
n1 = 0.74043 n2 = 0.74043 n_pos = 1.300000e+00 v1#branch = -50.0uA v2#branch = -50.0uA (v2#branch/v1#branch) = 1.0
And out relevant transistors' device parameters at the DC OP (re-formatted for display):
device m2 m1 model pmos pmos gm 387.93 uS 387.93 uS rds 805.91 kR 805.91 kR id 50.0 uA 50.0 uA vgs 0.55956 V 0.55956 V vds 0.55957 V 0.55957 V vth 0.33704 V 0.33704 V vdsat 0.22458 V 0.22458 V
As seen given our equal Vds for both source and mirror transistors, both branches are very well matched in performance.
DC Analysis (Sweep)
Measuring the variation of the mirrored output current under different applied loads. We are applying a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments. We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)
As can bee seen our current matching has degraded given finite Rout of the output transistor.
For the Simple PMOS Current Mirror above:
- The absolute minimum voltage needed for the mirror to be in the saturation region is its Vdsat (roughly a Veff) at the nominal 50uA mirror current i.e:
- Vmin_abs = Vdsat = 0.22458V
- However in practice the current mirror requires approximately at least a 0.35V voltage across it to be operational with maximum Rout (this can be seen from the plot above). Lower required voltages may be achieved through the use of larger width devices to yield lower Veff at the cost of larger areas.
- The variation of the drain current with changes in load voltage is as follows:
- Error Measurement: Variation of 49.581uA to 50.695uA over a linear operating range of 0.95 to 0V. This is equivalent to an error of 1.114uA or 2.228% relative to our current reference.
Figures of Merit
Output Resistance Rout: 852.78kΩ (measured from 0.95 to 0V linear range): Note this is consistent with the output resistance (rds) from device parameters from our operating point above.
Compliance Voltage: 0.35V (relative from VDD)
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.