The ubiquitous current mirror is used extensively for the biasing of Analog ICs. Much like in other mirrors, the NMOS current mirror replicates (or mirrors) the current from the main current source branch into any other branch. The mirrored current is often scaled by integer ratios (by transistor sizing) to the desired bias value for that particular branch.

A simple current mirror can be constructed by placing two back to back NMOS FETs. The first transistor on the reference branch has it’s drain and gate tied together in a “diode connected” fashion.

Alternatively, the reference transistor can be more insightfully seen as a small analog calculator, it allows us to find out the gate voltage needed to yield a desired bias current (an I/V converter) for a particularly sized transistor, using the transistor this way circumvents having to calculate analytically what this voltage would need to be. This known voltage can then be used to bias matched transistors to generate the desired mirrored current in other branches.

Design Procedure[edit]

The general design procedure for a simple mirror starts from the provided design requirements.

• Supply voltage
• Ouput current
• Input current
• Scaling multiplier (Iout/Imin)
• Output resistance (minimum required)
• Compliance voltage (given headroom requirements)
• Current mismatch

From the supply and the required headroom swing, we can calculate the maximum effective voltage we can afford for our mirror. (recall we want to maximize Veff in order to help minimize current mismatch.)

With the value for Veff, can start the preliminary design.

In the reference branch, keeping Iref constant and the width proportional to the device length (e.g. ~2xL by using two fingers or multiplier is a good start), increase our L until we meet our Veff setpoint.

Now, head to the mirror branch, set the L same as that used for the ref branch and scale W to the necessary K scale ratio (use multiplier for better matching, alternatively matched sized fingers).

Measure output mirror results of design:

• Measured Rout
• Measured K
• Measured Compliance
• Measure Statistical mismatch.

At this point we can start the design iterations,

If Rout is not met but we have enough swing margin, increase length for the ref and mirror to increase Rout. Otherwise if Rout not met and swing headroom is limited, move to enhanced Rout circuit progressions.

If mismatch is not met but we have enough swing margin, increase Veff via larger common length. Otherwise if swing headroom limited, increase area (improves mismatch) while keeping Veff constant by increasing W and L but keeping W/L ratio of transistor constant.

Else if swing is not met but we have some mismatch margin, decrease Veff by increasing W/L for both ref and mirror branches keeping proportionality. Otherwise if no mismatch margin, increase overall area by increasing W and L but keeping W/L ratio of transistor constant.