Current mirrors are used extensively for the biasing of analog integrated circuits, as active loads or also as part of current DACs. Their function is to replicate (or mirror) the current from the main current source branch into any other branch. The mirrored current is often scaled by integer ratios (by transistor sizing) to the desired bias value for that particular branch. Current mirrors are especially well suited to integrated circuits, due to the fine control over device matching properties available in integrated circuits (as opposed to that possible in discrete or hybrid implementations).
Much like for current sources, the ideal mirror must have an exact relative match between the output and reference current, and present an infinite output resistance to it's load -- meaning it should maintain the desired current output regardless of fluctuations in output voltage. The properties governing the performance of mirrors are discussed in more detail below.
A measure of the (non-ideal) current variation due to changes in load voltage.
It can be calculated as the change in output voltage divided by the change in output current.
The greater the output resistance of the current mirror, the less current variation with collector voltage (same current regardless of load), the better the performance of the circuit.
R_out = (delta_v) / (delta_i)
Compliance voltage (for current mirrors)
A measure of the minimum load (or output) voltage across the mirror for which it can maintain a constant current.
The closer to the supply rails the current mirror can operate, the better the compliance range, the better the performance of the circuit.
Scale ratio (k)
How does one scale output currents?
Given a bipolar current mirror, how does one scale output currents?
The current ratio is determined by increasing or decreasing the geometry of one of the reference or mirror branch transistors. More specifically for a bipolar transistor the ratio is determined by the size of the emitter – the active emitter length. This is accomplished by increasing the number (and size) of identical emitter diffusions as well as the number (and size) of the surrounding base diffusions, subsequently the single collector diffusion is increased proportionally in size (but not in number) to support larger currents.
- Scale Up: By increasing the number of identical emitters to say three, hence you multiply the output current by a factor of three relative to the current reference.
- Scale Down: By increasing the number of identical emitters to say three for the reference, hence you divide the output current by a factor of three.
Any ratio is possible by varying the emitter length of one of the current matching transistors. Keep in mind however that the base current of the output mirror will change proportionally with the scaled collector current and this will have an effect in the base current error of the mirror.
Given a MOS current mirror, how does one scale output currents?
One can scale the output current by varying the relative channel widths for the output mirror versus the reference branch transistors. However a better alternative is to use multiple identical devices in parallel which provides better matching.
Generating multiple currents (multiple mirror branches)
Given a single current reference, how does one generate multiple matched currents to be used for different circuit-blocks in an integrated circuit?
In the simplest case you can take the simple BJT Current Mirror and connect additional transistors in parallel – their bases tied together. Then, for every output transistor you can connect their individual collectors to different circuit-blocks.
There is a problem however, the more output transistors you add in parallel, the larger the base current error of the mirror. To remedy this error, you can add an additional current buffer emitter-follower transistor, this transistor provides the base current for all the current matching transistors from the power supply instead (with a very small base current taken from the reference). Now you can add a large number of output transistors with a very minor influence to the reference current.
On the other hand, this extra transistor introduces a small error: the collector voltages are no longer matched. We can partially compensate for this by adding emitter resistors (negative feedback) as explained in the Emitter Resistors (Negative Feedback) circuit entry below.
MOS devices do not have a DC gate current which fortunately means we can add as many output transistor devices as we want.
The only error to be concerned about is the current output dependence with drain voltage. To compensate for this error, we can explore some of the techniques explored below e.g. adding source resistors (negative feedback) or using a Wilson Current Mirror topology, a better alternative for MOS devices however, is to add a different cascode stage at the output of each mirror.
For MOS devices the current mismatch error is measured first nominally as the difference between the simulated output current and the desired current divided by the nominal desired current -- hence resulting in a current mismatch error ratio. It is also measured statistically (a monte carlo simulation is used for this purpose) to model real-world process variations over many runs (>> 100 runs are used, with 1000 runs being common).
The statistical current mismatch is expressed as the standard deviation of the error between simulated and nominal currents for all statistical sample runs (further normalized over the nominal current to attain the error ratio) as shown in the equation below. The current mismatch error decreases with the square root of the device area and also decreases proportionally with the transconductor efficiency gm/Id -- or said otherwise the current mismatch decreases proportionally with increasing Veff overdrive (as gm/Id = 2/Veff) in active. Operating with high Veff overdrives (operating the transistor in strong inversion) means we can attain the best matching but incur in a reduced headroom penalty, hence often times (and specially given advanced nodes with low supplies) a combination of an adequately high Veff biasing (typically a couple hundred mV), together with a larger device area is used to meet the necessary matching and headroom/compliance specs.
For most formal designs, normally a maximum current mismatch error (over one or two standard deviations) is given as a design spec.
Current Mirror Design Specs
In the real world current mirrors are designed to meet required design specifications, the key specs for a practical current mirror are the following:
- Output current (Iout): The desired mirrored (likely scaled) current.
- Provided as a requirement.
- Reference current (Iref): The available reference current.
- Given or flexible to designer.
- Scale ratio (K): The scale ratio from the reference current.
- K = Iout_max / Iref
- Often we want to know the maximum scale ratio to get a sense for range of practical device areas from reference to mirror branches.
- Calculated from known values.
- Output resistance (Rout): An inverse measure of the (non-ideal) current variation due to changes in load voltage.
- The larger Rout the better.
- A minimum Rout is often provided as a requirement.
- Compliance voltage: Minimum voltage needed across mirror to keep devices in active. (alternatively can also be expressed in terms of headroom)
- The smaller the better. (i.e. the largest allowed headroom the better)
- Largely governed by the min effective voltage necessary for transistors constituting the mirror.
- A minimum compliance voltage requirement is often given in order to meet output swing headroom at output node.
- Current Mismatch: how closely the output current matches the reference current, often measured at:
- DC Operating point
- Worst case over corner's simulations,
- Variance over statistical montecarlo simulation.
- Max current variation over 2 or 3σ often provided as a requirement to maintain performance of biased blocks after fabrication.
The degree to which a current mirror topology can meet specs and attain the largest output resistance and lowest compliance voltage and mismatch while considering complexity, area and power consumption largely determines it's performance in practice.
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (page 3-5 to 3-7)
- Chapter 1 (page 1-19)
- T. Chan Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd ed. Wiley, 2011.
- Chapter 2.3.3