NMOS 3T resistor-biased cascoded current mirror
As noted in the reference book (refer to page 3-7), one alternative commonly used to reduce the output current dependence with drain voltage for the simple MOS current mirror is to use a simple cascode stage. (We have kept the sizes for all MOS devices in line with our book reference).
The circuit below is the simplest resistor-biased cascoded mirror, it yields good rout performance and flexibility of cascode bias. This is the 3T version of the traditional 4T resistor-biased cascoded current mirror, we employ the resistor directly to bias the cascode.
For this topology, M2 will set the Vgs needed for M3 in order to enforce the mirrored current: hence the Vgs of M3 is held relatively constant. For this reason we size the resistor in order to raise the Vg of M3 such that given its fixed Vgs the voltages at the drain of M2 and M1 are relatively the same: for best current mirror matching.
Keep in mind, while this topology saves one transistor, it is simple to implement, and generally works well: there are a couple of notes worth mentioning.
This topology is not fully matched symmetrically hence over PVT the VDS over the bias and mirror devices will not track as closely to each other as with the 4T configuration, which depending on the rout of the mirror may lead to a larger current mirror output error (note there will still be some tracking as any bias voltage change will show up at the cascode bias as well). With adequate mirror rout the output current variation over PVT may not be an issue as long as the mirror device remains in sat, but it's important to keep this in mind.
Additionally, this traditional topology, has one knob which can be useful at times. The advantage of using R1 is that one can have finer control over the gate voltage of M3: as M3 is a source follower we have direct control over the VDS of our mirror M2 and can trade-off current match for headroom.
For example by reducing the value of R1 we can reduce the M2 mirror VDS to have a slightly larger load headroom at the cost of a worse current match (since the VDS of M1 and M2 now differ), taking VDS further down to M2's minimum VDsat value maximizes headroom but also trades-off output resistance. On the other hand R1 can be used to match the VDS of M1 and M2 and hence improve current match, going further one can allow some sat margin for M2 to place it in the area of maximum r_out; both at the cost of load headroom.
In applications where a small systematic current error from bias to source branches can be tolerated or is accounted for, one can attain a wide-swing (low-headroom) configuration by lowering the vds of M2 by design, such a tradeoff can in principle be controlled dynamically (tunable R or M3) depending on the output compliance needs.
One of course can employ alternative means of cascode bias generation which forgo the use of resistors (as will be shown on other posts) but alas this often comes with a performance or power consumption penalty. In other words, if area is available and rout is important, sometimes simple is best.
As with other cascoded current mirrors the rout is enhanced by the gain of the cascode transistor. Hence the rout of the output branch is proportional to:
r_out = ro2 x a3 = ro2 x (gm3 x ro3)
* dev <nets> <values> * ----------------------------------- I1 n_pos n3 50uA V1 n_pos 0 1.3V V2 n2 0 0.65V R1 n3 n1 10.7kΩ M1 n1 n1 0 0 nmos W=20u L=3u M2 n4 n1 0 0 nmos W=20u L=3u M3 n2 n3 n4 0 nmos W=10u L=0.35u
Operating Point Analysis
Operating point DC measurement results (re-formatted for display):
n1 = 0.520 n2 = 0.650 n3 = 1.055 n4 = 0.520 n_pos = 1.3 v1#branch = -50 uA v2#branch = -49.979 uA (v2#branch/v1#branch) = 0.99957
And our relevant transistors' device parameters at the DC OP (re-formatted for display):
device m3 m2 m1 model nmos nmos nmos gm 836.748 uS 556.725 uS 556.723 uS rds 29.3 kR 874.62 kR 874.4 kR id 49.979 uA 49.984 uS 49.984 uA vgs 0.534 0.520 0.520 vds 0.129 0.520 0.520 vth 0.509 0.388 0.388 vdsat 0.081 0.14 0.14
As seen given our equal Vds for both source and mirror transistors, both branches are very well matched in performance.
DC Analysis (Sweep)
For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments.
We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)
Monte Carlo Analysis
In our Montecarlo analysis, we are measuring the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistor parameters when added together can affect the performance of the overall circuit.
The Monte Carlo simulation was performed for 100 runs with a sigma value of 3. Note this is an educational kit, hence here we are just composing an arbitrary distribution by specifying a variation equivalent to 3 sigma (that yields a current mismatch of roughly +/- 1%). In a real kit, the variation would be obtained from foundry empirically measured data for a given process -- given a desired sigma spec and device parameter.
As per our book references, for MOS transistors: It is important to model variations of the threshold voltage, transconductance and capacitances. However, these parameters do not match one-to-one with the SPICE BSIM4 model parameters, thus we have chosen key BSIM4 parameters which affect directly the threshold voltage, transconductance and capacitances of MOS devices, mainly: vth0, u0, toxm (for bsim4), wint and lint.
For the cascoded current mirror, we can make the following observations
- The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.14 + 0.081 >> 0.221
- However as shown with the current sizing, the mirror requires at least ~0.5 load voltage to be yield its maximum Rout. (seen from the plot above where the slope is linear).
- Error Measurement: We see a variation of 49.92uA to 49.98uA over a linear operating range of 0.5 to 1.3V. This is equivalent to an error of 66.1nA or 0.132% relative to our reference.
Figures of Merit
Output Resistance Rout: 18.911MΩ (measured from 0.5 to 1.3V linear range).
Compliance Voltage Vmin: ~0.5V (from ground)
|Topology||Vmin (V)||Compliance Voltage (V)||r_out (kΩ)||Current Consumption (uA)||Area (um^2)|
|NMOS Source Degenerated||0.3815||0.45||1521||50||20 + 2 x A_r3k|
|NMOS 3T Res-biased Cascoded||0.221||0.5||18911||50||123.5 + 1 x A_r10p7k|
As noted above, we have chosen the resistance R1 to match the voltages at the drains of both M1 and M2 for best current match (at the cost of headroom), we can optimize for a different performance goal by changing the resistance in the bias branch accordingly.
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-7)
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.