PMOS 3T resistor-biased cascoded current mirrors
Note on sizing: we have aimed to maintain the absolute minimum voltage of the mirror consistent with the simple PMOS current mirror article to allow for comparison across topologies. In addition, we also maintained the device lengths consistent with those employed in the NMOS 3T resistor-biased cascoded current mirror to allow for comparisons across device types when possible. Because of these 2 constrains, we had to make our device widths (very) large. In practice, given this particular PDK, one would instead opt to relax the absolute minimum voltage constraint for the PMOS stack -- relative to the NMOS stack.
Schematic Diagram[edit]
Circuit Netlist[edit]
* dev <nets> <values> * ----------------------------------- I1 n3 0 50uA V1 vp 0 1.3V V2 vp n2 0.65V R1 n1 n3 8.73kΩ M1 n1 n1 vp vp pmos W=220u L=3u M2 n4 n1 vp vp pmos W=220u L=3u M3 n2 n3 n4 vp pmos W=110u L=0.35u
SPICE Simulations[edit]
Operating Point Analysis[edit]
Operating point DC measurement results (re-formatted for display):
n1 = 0.847 n2 = 0.650 n3 = 0.411 n4 = 0.847 vp = 1.3 v1#branch = 50 uA v2#branch = -50.0 uA (v2#branch/v1#branch) = 1.00
And our relevant transistors' device parameters at the DC OP (re-formatted for display):
device m3 m2 m1 model pmos pmos pmos gm 959.654 uS 624.766 uS 624.766 uS rds 90.643 kR 743.69 kR 743.69 kR id 50 uA 50 uA 50 uA vgs 0.436 V 0.453 V 0.453 V vds 0.197 V 0.453 V 0.453 V vth 0.423 V 0.337 V 0.337 V vdsat 0.083 V 0.140 V 0.140 V
As seen given our close Vds for both source and mirror transistors, both branches are very well matched in performance.
DC Analysis (Sweep)[edit]
For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 1.3V to 0V in 0.05V increments.
We are plotting the output current magnitude vs drain voltage.
Monte Carlo Analysis[edit]
In our Montecarlo analysis, we are measuring the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistor parameters when added together can affect the performance of the overall circuit (please refer to the NMOS counterpart article for additional setup details for this simulation).
Results[edit]
For the cascoded current mirror, we can make the following observations
- The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.140 + 0.083 >> 0.223
- However as shown with the current sizing, the mirror output can go up to maximum 0.8V (at least ~0.5 vload voltage relative to vp) to yield its maximum Rout. (seen from the plot above where the slope is linear).
- Error Measurement: We see a variation of 50.004uA to 49.984uA over a linear operating vload range of 0 to 0.8V. This is equivalent to an error of 20nA or 0.04% relative to our reference.
Figures of Merit[edit]
Output Resistance Rout: 40MΩ (measured from 0 to 0.8V linear range).
Compliance Voltage Vload min: ~0.5V (from VP)
In summary,
| Topology | Vmin (V) | Compliance Voltage (V) | r_out (kΩ) | Current Consumption (uA) | Area (um^2) |
|---|---|---|---|---|---|
| Simple PMOS | 0.225 | 0.35 | 852.78 | 50 | 200 |
| PMOS Source Degenerated | 0.3536 | 0.45 | 2148 | 50 | 200 + 2 x A_res |
| PMOS 3T Res-biased Cascoded | 0.221 | 0.5 | 40000 | 50 | 1,358 + 1 x A_r8p73k |
References[edit]
- Chapter 3 (pages 3-7)
Toolchain[edit]
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.
