NMOS self-biased cascoded current mirror
In this topology we can forgo the need to use an additional thin diode to generate our cascode bias. Instead we can make use of the input branch bias voltage and place a cascode in-between with its vgs setting the vds of our bias and mirror devices. This topology also has the benefit of being fully symmetrical, being advantageous in reducing any systematic offset that may arise otherwise.
The simplicity of this topology comes at a cost however: to be able to re-use the input branch diode voltage as a cascode bias, we need to make the input diode W/L thinner to raise this bias (at least until veff is larger than the vdsat_min, and larger if random mismatch needs to be reduced), in addition we need to make use of a wide cascode to reduce the vgs across it and allow enough sat margin for the bias and mirror devices. While this topology can be useful in many application the above shortcomings can sometimes over-constrain the design choices and result in either an impractically large area for the cascode or insufficient sat margin for the mirror (to allow it to be on the performance range of the r_out curve).
One interesting result of the reasoning above is that this topology becomes more useful in cases where we can make use of large W/L ratios to fit our cascode (with a low source follower Vgs), this can make this topology more useful in modern processes where we can attain large W/L ratios simply due to the reductions in gate lengths. The ideal practical scenario arises when (due to our large W/L wide cascode) we are able to leave roughly 100mV or slightly more of sat margin for the bias/mirror devices: which places the mirror slightly away from the triode/sat knee in the Ids vs Vds curve and into the r_out performance part of the curve.
For our particular sizing chosen below, we have aimed to maintain the minimum vdsat of the overall output plus mirror branch: to roughly match that of our previous cascoded mirrors to allow for comparison. Furthermore, we have kept the cascode width within practical size limits; although we would like to reduce further the cascode Vgs to increase the mirror sat margin, it really does not make much practical sense to opt for a wider device. This means we are operating our mirror with a minimum vdsat margin which puts us close to the triode/sat knee and hence hurts our rout performance.
As can be seen from the sizing argument above, the decision to use this topology is very technology dependent and while it is not as advantageous in this particular technology, it can be superior in other cases.
* dev <nets> <values> * ----------------------------------- I1 vp n1 50uA V1 vp 0 1.3V V2 n2 0 0.5957451V M1 n3 n1 0 0 nmos W=10u L=3u M2 n4 n1 0 0 nmos W=10u L=3u M3 n2 n1 n4 0 nmos W=100u L=0.35u M4 n1 n1 n3 0 nmos W=100u L=0.35u
Operating Point Analysis
Operating point DC measurement results (re-formatted for display):
n1 = 0.5957 n2 = 0.5957 n3 = 0.2433 n4 = 0.2433 v1#branch = -50.0 uA v2#branch = -49.9751 uA vp = 1.3 (v2#branch/v1#branch) = 0.9995
And our relevant transistor' device parameters at the DC OP (re-formatted for display)
device m4 m3 m2 m1 model nmos nmos nmos nmos gm 1.1197 mS 1.1197 mS 389.696 uS 389.696 uS gds 172.62 kR 172.62 kR 56.19 kR 56.19 kR id 49.9752 uA 49.9752 uA 49.9812 uA 49.9812 uA vgs 0.3524 V 0.3524 V 0.5957 V 0.5957 V vds 0.3524 V 0.3524 V 0.2433 V 0.2433 V vth 0.4478 V 0.4478 V 0.3880 V 0.3880 V vdsat 0.0477 V 0.0477 V 0.2017 V 0.2017 V
As mentioned in this article's introduction, we are taking a r_out penalty in our mirror (M2) due to having too low of a sat margin across it (sat margin ~ 41.6mV), ideally we would like to increase our sat margin > 100m to be on the r_out performance part of the curve (in addition one needs to consider the minimum sat margin carefully to maintain performance over PVT).
DC Analysis (Sweep)
For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments.
We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)
Monte Carlo Analysis
In our Montecarlo analysis, we are measuring the effect of transistors’ random mismatch on the output current of our mirror (i.e. how small random variations in individual transistor parameters when added together can result in an overall output current error).
Further details concerning Montecarlo simulation settings have been described under the NMOS 3T resistor-biased cascoded current mirror article and also apply here.
For the self-biased cascoded current mirror, we can make the following observations
- The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.2017 + 0.0477 = 0.249
- However as shown with the current sizing, the mirror requires at leas ~0.4 load voltage to yields its maximum Rout. (seen from the plot above where the slope is linear).
- Error measurement: We see a variation of 49.95676uA to 50.02394uA over a performance operating range of 0.4 to 1.3V. (keep in mind this is only for the typical corner)
Figures of Merit
Output Resistance Rout: 13.40MΩ (measured from 0.4 to 1.3V linear range).
Compliance voltage vmin: ~0.4V (from ground)
|Topology||Vmin (V)||Compliance Voltage (V)||r_out (kΩ)||Bias Current (uA)||Area (um^2)|
|NMOS Source Degenerated||0.3815||0.45||1521||50||20 + 2 x A_r3k|
|NMOS 3T Res-biased Cascoded||0.221||0.5||18911||50||123.5 + 1 x A_r10p7k|
|NMOS Diode-biased Cascoded||0.226||0.4||43500||100||139|
|NMOS Self-biased Cascoded||0.249||0.4||13400||50||130|
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-8)
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.