NMOS self-biased cascoded current mirror

In this topology we can forgo the need to use an additional thin diode to generate our cascode bias. Instead we can make use of the input branch bias voltage and place a cascode in-between with its vgs setting the vds of our bias and mirror devices. This topology also has the benefit of being fully symmetrical, being advantageous in reducing any systematic offset that may arise otherwise.

The simplicity of this topology comes at a cost however: to be able to re-use the input branch diode voltage as a cascode bias, we need to make the input diode W/L thinner to raise this bias (at least until veff is larger than the vdsat_min, and larger if random mismatch needs to be reduced), in addition we need to make use of a wide cascode to reduce the vgs across it and allow enough sat margin for the bias and mirror devices. While this topology can be useful in many applications, the above shortcomings can sometimes over-constrain the design choices and result in either an impractically large area for the cascode or insufficient sat margin for the mirror (to allow it to be on the performance range of the r_out curve).

One interesting result of the reasoning above is that this topology becomes more useful in cases where we can make use of large W/L ratios to fit our cascode (with a low source follower Vgs), this can make this topology more useful in modern processes where we can attain large W/L ratios simply due to the reductions in gate lengths. The ideal practical scenario arises when (due to our large W/L wide cascode) we are able to leave roughly 100mV or slightly more of sat margin for the bias/mirror devices: which places the mirror slightly away from the triode/sat knee in the Ids vs Vds curve and into the r_out performance part of the curve.

For our particular sizing chosen below, we have aimed to maintain the minimum vdsat of the overall output plus mirror branch: to roughly match that of our previous cascoded mirrors to allow for comparison. We have chosen a W/L for the cascode to leave roughly 100mV of sat margin for our mirror (we could have increased the mirror's sat margin further but this would have resulted in excessive W/L ratios). Lastly, we have opted for using Lmin for the cascode to keep its width within practical limits (this comes at the cost of lower r_out but results in a practical design for this PDK.

Schematic Diagram

Circuit Netlist

* dev <nets>     <values>                                                                         
* -----------------------------------                                                                
I1    vp n1      50uA                                                                                
V1    vp 0       1.3V                                                                                
V2    n2 0       0.5726419V                                                                          
M1    n3 n1 0 0  nmos W=12u  L=3u                                                                    
M2    n4 n1 0 0  nmos W=12u  L=3u                                                                    
M3    n2 n1 n4 0 nmos W=80u L=0.130u                                                                 
M4    n1 n1 n3 0 nmos W=80u L=0.130u                                                                

SPICE Simulations

Operating Point Analysis

Operating point DC measurement results (re-formatted for display):

n1 = 5.726419e-01
n2 = 5.726419e-01
n3 = 2.888442e-01
n4 = 2.888442e-01
v1#branch = -5.00000e-05
v2#branch = -4.99772e-05
vp = 1.300000e+00
(v2#branch/v1#branch) = 9.995447e-01

And our relevant transistor' device parameters at the DC OP

    device                    m4                    m3                    m2
     model                  nmos                  nmos                  nmos
        gm            0.00122477            0.00122477           0.000438655
      gmbs           0.000297133           0.000297133           0.000125152
       gds            9.3764e-05            9.3764e-05           5.45135e-06
        id           4.99772e-05           4.99772e-05           4.99827e-05
       vgs              0.283798              0.283798              0.572642
       vds              0.283798              0.283798              0.288844
       vbs             -0.288844             -0.288844           5.70351e-13
       vth              0.440434              0.440434              0.388024
     vdsat             0.0407983             0.0407983              0.184518
---
    device                    m1
     model                  nmos
        gm           0.000438655
      gmbs           0.000125152
       gds           5.45135e-06
        id           4.99827e-05
       vgs              0.572642
       vds              0.288844
       vbs           5.70351e-13
       vth              0.388024
     vdsat              0.184518

DC Analysis (Sweep)

For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)

Monte Carlo Analysis

In our Montecarlo analysis, we are measuring the effect of transistors’ random mismatch on the output current of our mirror (i.e. how small random variations in individual transistor parameters when added together can result in an overall output current error).

Further details concerning Montecarlo simulation settings have been described under the NMOS 3T resistor-biased cascoded current mirror article and also apply here.

Results

For the self-biased cascoded current mirror, we can make the following observations

• The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.1845 + 0.0408 = 0.2253

• However as shown with the current sizing, the mirror requires at leas ~0.4 load voltage to yields its maximum Rout. (seen from the plot above where the slope is linear).

• Error measurement: We see a variation of 49.9150uA to 50.1514uA over a performance operating range of 0.4 to 1.3V. (keep in mind this is only for the typical corner)

Figures of Merit

Output Resistance Rout: 3.807MΩ (measured from 0.4 to 1.3V linear range).

Compliance voltage vmin: ~0.4V (from ground)

In summary,

Current Mirrors Performance Summary

Topology	Vmin (V)	Compliance Voltage (V)	r_out (kΩ)	Bias Current (uA)	Area (um^2)
Simple NMOS	0.226	0.35	869.17	50	20
NMOS Source Degenerated	0.3815	0.45	1521	50	20 + 2 x A_r3k
NMOS 3T Res-biased Cascoded	0.221	0.5	18911	50	123.5 + 1 x A_r10p7k
NMOS 4T Res-biased Cascoded	0.226	0.4	43605	50	127 + 1 x A_r4p4k
NMOS Diode-biased Cascoded	0.226	0.4	43500	100	139
NMOS Self-biased Cascoded	0.225	0.4	3807	50	92.8

Note the self-biased case has a few interesting features. Maintaining the same compliance, we can attain a greater r_out at the only cost of a large W/L cascode. Even using an Lmin cascode to minimize area still results in an r_out comparable with the source degenerated case without the headroom penalty nor the area penalty of other performance mirrors. Furthermore, the arguments for this implementation become stronger on modern processes as Lmin continues scaling down.

Also note one could come up with a useful figure of merit that takes into account performance and weighted cost factors, something like FoM ~ r_out / (a*vmin x b*i_bias x c*area) to allow to compare across implementations for a particular application r_out and given weights (but it's not so useful here given unknown area of resistors on layout).

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (pages 3-8)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.