NMOS 4T resistor-biased cascoded current mirror: Difference between revisions
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* PTM 130nm CMOS [https://github.com/ICclopedia/ICclopedia/blob/master/device_parameter_libraries/cmos_ptm_asu_130nm_tt.spice SPICE models]. |
* PTM 130nm CMOS [https://github.com/ICclopedia/ICclopedia/blob/master/device_parameter_libraries/cmos_ptm_asu_130nm_tt.spice SPICE models]. |
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[[Category:MOS resistor-biased cascoded current mirrors]] |
[[Category:MOS resistor-biased cascoded current mirrors|3]] |
Revision as of 18:05, 21 May 2023
Schematic Diagram
Circuit Netlist
* dev <nets> <values> * -----------------------------------
SPICE Simulations
Operating Point Analysis
DC Analysis (Sweep)
File:NMOS 4T cascoded current mirror simulation dc analysis.svg
Monte Carlo Analysis
File:NMOS 4T cascoded current mirror simulation mc analysis.svg
Results
Figures of Merit
References
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-7)
Toolchain
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.