NMOS 4T resistor-biased cascoded current mirror

Schematic Diagram

Circuit Netlist

* dev <nets>        <values>                                                                         
* -----------------------------------                                                                

SPICE Simulations

DC Analysis (Sweep)

File:NMOS 4T cascoded current mirror simulation dc analysis.svg

Monte Carlo Analysis

File:NMOS 4T cascoded current mirror simulation mc analysis.svg

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (pages 3-7)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.