NMOS 4T resistor-biased cascoded current mirror
As discussed in other articles, there are different ways we can generate our cascode bias voltage, one way to do this is via use of an additional current branch and a thin diode-connected device (as shown in the NMOS diode-biased cascoded current mirror article), another more traditional alternative (as shown on the NMOS 3T resistor-biased cascoded current mirror) is by making use of a resistance in-branch to generate the cascode bias (one shortcoming of the latter is the 3T asymmetry which leads to systematic offset between bias and mirror branches). The 4T topology below overcomes this asymmetry (among other benefits) and is usually used instead as it can be very well matched in practice.
In general, the 4T resistor-biased topology is typically a good fit in cases where one has access to high-R resistors in the technology kit and can afford the area needed for the resistor. In such a scenario this traditional 4T R-based topology can be superior as it allows for good control for the cascode bias, it saves the additional current needed for the diode and in many cases leads to less variability over PVT (although this depends on many factors).
As before our cascoded rout is approximately given by:
r_out = ro2 x a3 = ro2 x (gm3 x ro3)
* dev <nets> <values> * ----------------------------------- I1 n_pos n3 50uA V1 n_pos 0 1.3V V2 n2 0 0.5210533V R1 n3 n1 4.4kΩ M1 n4 n1 0 0 nmos W=20u L=3u M2 n5 n1 0 0 nmos W=20u L=3u M3 n2 n3 n5 0 nmos W=10u L=0.35u M4 n1 n3 n4 0 nmos W=10u L=0.35u
Operating Point Analysis
Operating point DC measurement results (re-formatted for display):
n1 = 5.210533e-01 n2 = 5.210533e-01 n3 = 7.410507e-01 n4 = 2.673797e-01 n5 = 2.673795e-01 vp = 1.300000e+00 v1#branch = -50.00 uA v2#branch = -49.98 uA (v2#branch/v1#branch) = 0.9996
And our relevant transistor' device parameters at the DC OP (re-formatted for display)
device m4 m3 m2 m1 model nmos nmos nmos nmos gm 859.89 uS 859.89 uS 552.844 uS 552.844 uS gds 150.089 kR 150.089 kR 218.435 kR 218.435 kR id 49.979 uA 49.980 uA 49.984 uA 49.984 uA vgs 0.4737 V 0.4737 V 0.5210 V 0.5210 V vds 0.2537 V 0.2537 V 0.2674 V 0.2674 V vth 0.4536 V 0.4536 V 0.3880 V 0.3880 V vdsat 0.0787 V 0.0787 V 0.1471 V 0.1471 V
DC Analysis (Sweep)
For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments.
We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)
Monte Carlo Analysis
In our Montecarlo analysis, we are measuring the effect of transistors’ random mismatch on the output current of our mirror (i.e. how small random variations in individual transistor parameters when added together can result in an overall output current error).
Further details concerning Montecarlo simulation settings have been described under the NMOS 3T resistor-biased cascoded current mirror article and also apply here.
For the cascode current mirror, we can make the following observations (note these are very similar to our diode-based cascoded design as we have tried to match bias and sizing to allow us to compare across).
- The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.147 + 0.079 >> 0.226
- However as shown with the current sizing, the mirror requires at least ~0.4 load voltage to yield its maximum Rout. (seen from the plot above where the slope is linear).
- Error Measurement: We see a variation of 49.97267uA to 49.99331uA over a performance operating range of 0.4 to 1.3V.
Figures of Merit
Output Resistance Rout: 43.60MΩ (measured from 0.4 to 1.3V linear range).
Compliance Voltage Vmin: ~0.4V (from ground)
|Topology||Vmin (V)||Compliance Voltage (V)||r_out (kΩ)||Bias Current (uA)||Area (um^2)|
|NMOS Source Degenerated||0.3815||0.45||1521||50||20 + 2 x A_r3k|
|NMOS 3T Res-biased Cascoded||0.221||0.5||18911||50||123.5 + 1 x A_r10p7k|
|NMOS 4T Res-biased Cascoded||0.226||0.4||43605||50||127 + 1 x A_r4p4k|
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-7)
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.