Category:Current mirrors: Difference between revisions

Current mirrors are used extensively for the biasing of analog integrated circuits or also as part of current DACs. Their function is to replicate (or mirror) the current from the main current source branch into any other branch. The mirrored current is often scaled by integer ratios (by transistor sizing) to the desired bias value for that particular branch. Current mirrors are especially well suited to integrated circuits, due to the fine control over device matching properties available in integrated circuits (as opposed to that possible in discrete or hybrid implementations).

Much like for current sources, the ideal mirror must have an exact relative match between the output and reference current, and present an infinite output resistance to it's load -- meaning it should maintain the desired current output regardless of fluctuations in output voltage.

Toward this end, in a real world current mirrors are designed to meet required design specifications, the key specs for a practical current mirror are the following:

• Output resistance (Rout): A measure of the (non-ideal) current variation due to changes in load voltage.
  • The larger the better.
  • A minimum Rout is often provided as a requirement.

• Compliance voltage: Minimum voltage needed across mirror to keep devices in active. (alternatively can also be expressed in terms of headroom)
  • The smaller the better. (i.e. the largest allowed headroom the better)
  • Largely governed by the min effective voltage necessary for transistors constituting the mirror.
  • A minimum compliance voltage requirement is often given in order to meet output swing headroom at output node.

• Current Mismatch: how closely the output current matches the reference current, often measured at:
  • DC Operating point
  • Worst case over corner's simulations,
  • Variance over statistical montecarlo simulation.
  • Max current variation over 2 or 3σ often provided as a requirement to maintain performance of biased blocks after fabrication.

The degree to which a current mirror topology can attain the largest output resistance and lowest compliance votlage and mismatch while considering complexity, area and power consumption largely determines it's performance in practice.