PMOS self-biased cascoded current mirror

From ICclopedia

Schematic Diagram[edit]

Circuit Netlist[edit]

I1    n1 0          50u                                                                              
V1    vp 0          1.3V                                                                             
V2    vp n2         0.5003101V                                                                       
M1    n3 n1 vp vp   pmos W=130u L=3u                                                                 
M2    n4 n1 vp vp   pmos W=130u L=3u                                                                 
M3    n2 n1 n4 vp   pmos W=800u L=0.130u                                                             
M4    n1 n1 n3 vp   pmos W=800u L=0.130u

SPICE Simulations[edit]

Operating Point Analysis[edit]

Operating point DC measurement results (re-formatted for display):

n1 = 7.996899e-01
n2 = 7.996899e-01
n3 = 1.019879e+00
n4 = 1.019879e+00
v1#branch = -5.00000e-05
v2#branch = -5.00000e-05
vp = 1.300000e+00
(v2#branch/v1#branch) = 9.999997e-01

And our relevant transistor' device parameters at the DC OP (re-formatted for display)

    device                    m4                    m3                    m2
     model                  pmos                  pmos                  pmos
        gm            0.00128558            0.00128559           0.000498746
      gmbs           0.000260195           0.000260198           0.000114188
       gds            0.00012353           0.000123531           5.45007e-06
        id           5.00005e-05           5.00011e-05                 5e-05
       vgs              0.220189              0.220189               0.50031
       vds              0.220189              0.220189              0.280121
       vbs             -0.280121             -0.280121           5.52225e-13
       vth              0.377584              0.377584              0.337024
     vdsat             0.0485558             0.0485558              0.176886


    device                    m1
     model                  pmos
        gm           0.000498746
      gmbs           0.000114188
       gds           5.45004e-06
        id                 5e-05
       vgs               0.50031
       vds              0.280121
       vbs           5.52003e-13
       vth              0.337024
     vdsat              0.176886

DC Analysis (Sweep)[edit]

For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 1.3V to 0V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage.

Monte Carlo Analysis[edit]

In our Montecarlo analysis, we are measuring the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistor parameters when added together can affect the performance of the overall circuit (please refer to the NMOS counterpart article for additional setup details for this simulation).


For the self-biased cascoded current mirror, we can make the following observations

  • The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.1769 + 0.0485 >> 0.225
  • However as shown with the current sizing, the mirror output can go up to maximum 0.9V (at least ~0.4 vload voltage relative to vp) to yield its maximum Rout (seen from the plot above where the slope is linear).
  • Error Measurement: We see a variation of 50.2130uA to 49.9546uA over a linear operating vload range of 0 to 0.9V. This is equivalent to an error of 258.4nA or 0.516% relative to our reference.

Figures of Merit[edit]

Output Resistance Rout: 3.483MΩ (measured from 0.4 to 1.3V linear range)

Compliance Voltage Vmin: ~0.4V (from VP)

In summary,

Current Mirrors Performance Summary
Topology Vmin (V) Compliance Voltage (V) r_out (kΩ) Current Consumption (uA) Area (um^2)
Simple PMOS 0.225 0.35 852.78 50 200
PMOS Source Degenerated 0.3536 0.45 2148 50 200 + 2 x A_res
PMOS 3T Res-biased Cascoded 0.221 0.5 40000 50 1,358 + 1 x A_r8p73k
PMOS 4T Res-biased Cascoded 0.221 0.4 37720 50 1,397 + 1 x A_r4k
PMOS diode-biased Cascoded 0.221 0.4 38140 50 1,520
PMOS Self-biased Cascoded 0.225 0.4 3483 50 983