PMOS diode-biased cascoded current mirror

Schematic Diagram

SPICE Simulations

Operating Point Analysis

Operating point DC measurement results (re-formatted for display)

n1 = 0.773
n2 = 0.650
n3 = 0.280
n4 = 0.777
n5 = 0.427
vp = 1.3
v1#branch = I1 + I2 = (-50) + (-50) 
v1#branch = -100uA
v2#branch = -49.996 uA
(v2#branch/50uA) = 0.9992

DC Analysis (Sweep)

Monte Carlo Analysis

Results

Figures of Merit

Output Resistance Rout:

Compliance Voltage Vmin:

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (pages 3-8)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.