# Circuit Netlist

```* dev <nets>        <values>
* -----------------------------------
I1    n5 0        50uA
I2    n3 0        50uA
V1    vp 0        1.3V
V2    vp n2       0.45334V
M1    n1 n5 vp vp pmos W=220u L=3u
M2    n4 n5 vp vp pmos W=220u L=3u
M3    n2 n3 n4 vp pmos W=110u L=0.35u
M4    n5 n3 n1 vp pmos W=110u L=0.35u
M5    n3 n3 vp vp pmos W=41u L=3u
```

# SPICE Simulations

## Operating Point Analysis

Operating point DC measurement results (re-formatted for display)

```n1 = 1.045
n2 = 0.847
n3 = 0.646
n4 = 1.045
n5 = 0.847
v1#branch = I1 + I2 = (-50) + (-50)
v1#branch = -100uA
v2#branch = -50uA
vp = 1.3
(v2#branch/v1#branch) = 1.0
```

And our relevant transistors' device parameters at the DC OP (re-formatted for display):

```device  m5        m4        m3        m2         m1
model   pmos      pmos      pmos      pmos       pmos
gm      275.6 uS  959.3 uS  959.2 uS  620.8 uS   620.8 uS
rds     1.095 MR  92.41 kR  92.41 kR  201.36 kR  201.35 kR
id      50 uA     50 uA     50 uA     50 uA      50 uA
vgs     0.654 V   0.399 V   0.399 V   0.453 V    0.453 V
vds     0.654 V   0.198 V   0.198 V   0.255 V    0.255 V
vth     0.337 V   0.390 V   0.390 V   0.337 V    0.337 V
vdsat   0.302 V   0.080 V   0.080 V   0.141 V    0.141 V
```

## DC Analysis (Sweep)

For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 1.3V to 0V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage.

## Monte Carlo Analysis

In our Montecarlo analysis, we are measuring the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistor parameters when added together can affect the performance of the overall circuit (please refer to the NMOS counterpart article for additional setup details for this simulation).

# Results

For the cascoded current mirror, we can make the following observations

• The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.141 + 0.080 >> 0.221
• However as shown with the current sizing, the mirror output can go up to maximum 0.9V (at least ~0.4 vload voltage relative to vp) to yield its maximum Rout (seen from the plot above where the slope is linear).
• Error Measurement: We see a variation of 50.0194uA to 49.9958uA over a linear operating vload range of 0 to 0.9V. This is equivalent to an error of 24nA or 0.05% relative to our reference.

## Figures of Merit

Output Resistance Rout: 38.14MΩ (measured from 0.4 to 1.3V linear range)

Compliance Voltage Vmin: ~0.4V (from VP)

In summary,

Current Mirrors Performance Summary
Topology Vmin (V) Compliance Voltage (V) r_out (kΩ) Current Consumption (uA) Area (um^2)
Simple PMOS 0.225 0.35 852.78 50 200
PMOS Source Degenerated 0.3536 0.45 2148 50 200 + 2 x A_res
PMOS 3T Res-biased Cascoded 0.221 0.5 40000 50 1,358 + 1 x A_r8p73k
PMOS 4T Res-biased Cascoded 0.221 0.4 37720 50 1,397 + 1 x A_r4k
PMOS diode-biased Cascoded 0.221 0.4 38140 50 1,520

Please keep in mind, the area figures for the diode-biased cascoded example above are not considering the area of devices needed to mirror the I1 to I2 current