PMOS diode-biased cascoded current mirror

Schematic Diagram

SPICE Simulations

DC Analysis (Sweep)

Monte Carlo Analysis

Results

Figures of Merit

Output Resistance Rout:

Compliance Voltage Vmin:

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (pages 3-8)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.