PMOS diode-biased cascoded current mirror

Schematic Diagram

SPICE Simulations

Operating Point Analysis

Operating point DC measurement results (re-formatted for display)

n1 = 0.773
n2 = 0.650
n3 = 0.280
n4 = 0.777
n5 = 0.427
vp = 1.3
v1#branch = I1 + I2 = (-50) + (-50) 
v1#branch = -100uA
v2#branch = -49.996 uA
(v2#branch/50uA) = 0.9992

And our relevant transistors' device parameters at the DC OP (re-formatted for display):

device  m5          m4         m3         m2          m1                                 
model   pmos        pmos       pmos       pmos        pmos                               
gm      120.844 uS  819.692 uS 775.238    445.312 uS  445.348 uS                         
gds     1.533 MR    169.36 kR  14.588 kR  885.61 kR   892.41 kR                          
id      50 uA       50 uA      49.996 uA  49.996 uA   50 uA                              
vgs     1.0199 V    0.492 V    0.496 V    0.527 V     0.527 V                            
vds     1.0199 V    0.346 V    0.127 V    0.523 V     0.527 V                            
vth     0.337  V    0.439 V    0.439 V    0.337 V     0.337 V                            
vdsat   0.601  V    0.108 V    0.110 V    0.198 V     0.198 V

DC Analysis (Sweep)

Monte Carlo Analysis

Results

Figures of Merit

Output Resistance Rout:

Compliance Voltage Vmin:

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (pages 3-8)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.