PMOS diode-biased cascoded current mirror: Difference between revisions
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== Operating Point Analysis == |
== Operating Point Analysis == |
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Operating point DC measurement results (re-formatted for display) |
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n1 = 7.730172e-01 |
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n2 = 6.500000e-01 |
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n3 = 2.801122e-01 |
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n4 = 7.765793e-01 |
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n5 = 4.270489e-01 |
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vp = 1.3 |
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v1#branch = I1 + I2 = (-50) + (-50) |
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v1#branch = -100uA |
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v2#branch = -49.996 uA |
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(v2#branch/50uA) = 0.9992 |
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== DC Analysis (Sweep) == |
== DC Analysis (Sweep) == |
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Revision as of 00:18, 21 November 2022
Schematic Diagram
SPICE Simulations
Operating Point Analysis
Operating point DC measurement results (re-formatted for display)
n1 = 7.730172e-01 n2 = 6.500000e-01 n3 = 2.801122e-01 n4 = 7.765793e-01 n5 = 4.270489e-01 vp = 1.3 v1#branch = I1 + I2 = (-50) + (-50) v1#branch = -100uA v2#branch = -49.996 uA (v2#branch/50uA) = 0.9992
DC Analysis (Sweep)
Monte Carlo Analysis
Results
Figures of Merit
Output Resistance Rout:
Compliance Voltage Vmin:
References
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-8)
Toolchain
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.
