PMOS diode-biased cascoded current mirror: Difference between revisions
From ICclopedia
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= Schematic Diagram = |
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We will follow NMOS format here. |
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[[File:PMOS_diode-biased_cascoded_current_mirror.svg|600px]] |
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= SPICE Simulations = |
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== Operating Point Analysis == |
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== DC Analysis (Sweep) == |
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[[File:PMOS_diode-biased_cascoded_current_mirror_dc_analysis.svg|800px]] |
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== Monte Carlo Analysis == |
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[[File:PMOS_diode-biased_cascoded_current_mirror_mc_analysis.svg|800px]] |
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= Results = |
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== Figures of Merit == |
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'''Output Resistance Rout''': |
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'''Compliance Voltage Vmin''': |
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= References = |
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* [http://www.designinganalogchips.com Designing Analog Chips (Hans Camenzind)] |
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** Chapter 3 (pages 3-8) |
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* [https://github.com/ICclopedia/ICclopedia/tree/master/current_mirrors/mos_diode-biased_cascoded_current_mirrors/pmos Project files]. |
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= Toolchain = |
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* ICclopedia [[Toolchain]]. |
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* PTM 130nm CMOS [https://github.com/ICclopedia/ICclopedia/blob/master/device_parameter_libraries/cmos_ptm_asu_130nm_tt.spice SPICE models]. |
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[[Category:MOS diode-biased cascoded current mirrors]] |
[[Category:MOS diode-biased cascoded current mirrors]] |
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Revision as of 23:14, 20 November 2022
Schematic Diagram
SPICE Simulations
Operating Point Analysis
DC Analysis (Sweep)
Monte Carlo Analysis
Results
Figures of Merit
Output Resistance Rout:
Compliance Voltage Vmin:
References
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-8)
Toolchain
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.
