NMOS 4T resistor-biased cascoded current mirror: Difference between revisions

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= Circuit Netlist =
= Circuit Netlist =


⚫
* dev <nets> <values>
* dev <nets> <values>
* -----------------------------------
* -----------------------------------
⚫
I1 n_pos n3 50uA
V1 n_pos 0 1.3V
V2 n2 0 0.5210533V
R1 n3 n1 4.4kΩ
M1 n4 n1 0 0 nmos W=20u L=3u
M2 n5 n1 0 0 nmos W=20u L=3u
M3 n2 n3 n5 0 nmos W=10u L=0.35u
M4 n1 n3 n4 0 nmos W=10u L=0.35u


= SPICE Simulations =
= SPICE Simulations =

Revision as of 01:35, 31 May 2023

Schematic Diagram

Circuit Netlist

* dev <nets>        <values>                                                                         
* -----------------------------------                                                                
I1    n_pos n3      50uA                                                                             
V1    n_pos 0       1.3V                                                                             
V2    n2    0       0.5210533V                                                                       
R1    n3    n1      4.4kΩ                                                                            
M1    n4    n1 0  0 nmos W=20u L=3u                                                                  
M2    n5    n1 0  0 nmos W=20u L=3u                                                                  
M3    n2    n3 n5 0 nmos W=10u L=0.35u                                                               
M4    n1    n3 n4 0 nmos W=10u L=0.35u

SPICE Simulations

Operating Point Analysis

DC Analysis (Sweep)

File:NMOS 4T cascoded current mirror simulation dc analysis.svg

Monte Carlo Analysis

File:NMOS 4T cascoded current mirror simulation mc analysis.svg

Results

Figures of Merit

References

Toolchain

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