PMOS source degenerated current mirror
From ICclopedia
Schematic Diagram[edit]
Circuit Netlist[edit]
* dev <nets> <values> * -------------------------- I1 n1 0 50uA V1 vp 0 1.3V V2 vp n2 0.71005V M1 n1 n1 n3 vp pmos w=100u l=3u M2 n2 n1 n4 vp pmos w=100u l=3u R1 vp n3 3kR R2 vp n4 3kR
SPICE Simulations[edit]
n1 = 0.5899 n2 = 0.5899 n3 = 1.15 n4 = 1.15 v1#branch = -50.0 v2#branch = -50.0 (v2#branch/v1#branch) = 1
Operating Point Analysis[edit]
device m2 m1 model pmos pmos gm 442.69 uS 442.69 uS rds 944.9 kR 944.9 kR id 50.0 uA 50.0 uA vgs 0.5600 V 0.5600 V vds 0.5600 V 0.5600 V vth 0.3689 V 0.3689 V vdsat 0.2036 V 0.2036 V
DC Analysis (Sweep)[edit]
Results[edit]
- The absolute minimum voltage needed for the mirror to be in the saturation region is it's Vdsat (roughly a Veff) plus the drop across the source resistor at the nominal 50uA mirror current i.e:
- Vmin_abs = 0.2036 + 0.150 > 0.3536 V
- However in practice the current mirror requires at least a 0.45V load voltage to be operational with its maximum Rout (this can be seen from the plot above where the slope is linear).
- Error Measurement: Variation of 49.7949uA to 50.1906uA over a linear operating range of 0.85 to 0. This is equivalent to an error of 0.3958uA or 0.7915% relative to our current reference.
Figures of Merit[edit]
Output Resistance Rout: 2.1478MΩ (measured from 0.85 to 0V linear range)
Compliance Voltage: 0.45V (relative from VDD)
In summary,
| Topology | Vmin (V) | Compliance Voltage (V) | r_out (kΩ) | Current Consumption (uA) | Area (um^2) |
|---|---|---|---|---|---|
| Simple PMOS | 0.225 | 0.35 | 852.78 | 50 | 200 |
| PMOS Source Degenerated | 0.3536 | 0.45 | 2148 | 50 | 200 + 2 x A_res |
References[edit]
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (page 3-3)
Toolchain[edit]
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.
