PMOS diode-biased cascoded current mirror

Schematic Diagram

Circuit Netlist

* dev <nets>      <values>                                                                         
* -----------------------------------                                                                
I1    n5 0        50uA                                                                               
I2    n3 0        50uA                                                                               
V1    vp 0        1.3V                                                                               
V2    vp n2       0.65V                                                                              
M1    n1 n1 vp vp pmos W=100u L=3u                                                                   
M2    n4 n1 vp vp pmos W=100u L=3u                                                                   
M3    n2 n3 n4 vp pmos W=50u  L=0.35u                                                                
M4    n5 n3 n1 vp pmos W=50u  L=0.35u                                                                
M5    n3 n3 vp vp pmos W=11u L=3u 

SPICE Simulations

Operating Point Analysis

Operating point DC measurement results (re-formatted for display)

n1 = 0.773
n2 = 0.650
n3 = 0.280
n4 = 0.777
n5 = 0.427
vp = 1.3
v1#branch = I1 + I2 = (-50) + (-50) 
v1#branch = -100uA
v2#branch = -49.996 uA
(v2#branch/50uA) = 0.9992

And our relevant transistors' device parameters at the DC OP (re-formatted for display):

device  m5          m4         m3         m2          m1                                 
model   pmos        pmos       pmos       pmos        pmos                               
gm      120.844 uS  819.692 uS 775.238    445.312 uS  445.348 uS                         
gds     1.533 MR    169.36 kR  14.588 kR  885.61 kR   892.41 kR                          
id      50 uA       50 uA      49.996 uA  49.996 uA   50 uA                              
vgs     1.0199 V    0.492 V    0.496 V    0.527 V     0.527 V                            
vds     1.0199 V    0.346 V    0.127 V    0.523 V     0.527 V                            
vth     0.337  V    0.439 V    0.439 V    0.337 V     0.337 V                            
vdsat   0.601  V    0.108 V    0.110 V    0.198 V     0.198 V

DC Analysis (Sweep)

For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 1.3V to 0V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage.

Monte Carlo Analysis

In our Montecarlo analysis, we are measuring the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistor parameters when added together can affect the performance of the overall circuit (please refer to the NMOS counterpart article for additional setup details for this simulation).

Results

For the cascoded current mirror, we can make the following observations

• The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.110 + 0.198 >> 0.308

• However as shown with the current sizing, the mirror output can go up to maximum 0.8V (at least ~0.5 vload voltage relative to vp) to yield its maximum Rout. (seen from the plot above where the slope is linear).

• Error Measurement: We see a variation of 49.924uA to 50.002uA over a linear operating vload range of 0.8 to 0V. This is equivalent to an error of 78nA or 0.156% relative to our reference.

Figures of Merit

Output Resistance Rout: 10.256MΩ (measured from 0.8 to 0V linear range)

Compliance Voltage Vmin: 0.8V (or ~0.5V from VP)

Please keep in mind the figures above are likely to be optimistic given we have not considered mirror performance over PVT (where we will expect a large variation from the diode based reference).

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (pages 3-8)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.