PMOS 4T resistor-biased cascoded current mirrors
Schematic Diagram[edit]
Circuit Netlist[edit]
* dev <nets> <values> * ----------------------------------- I1 n3 0 50uA V1 vp 0 1.3V V2 vp n2 0.45335V R1 n1 n3 4kΩ M1 n4 n1 vp vp pmos W=220u L=3u M2 n5 n1 vp vp pmos W=220u L=3u M3 n2 n3 n5 vp pmos W=110u L=0.35u M4 n1 n3 n4 vp pmos W=110u L=0.35u
SPICE Simulations[edit]
Operating Point Analysis[edit]
Operating point DC measurement results (re-formatted for display):
n1 = 8.466514e-01 n2 = 8.466500e-01 n3 = 6.466514e-01 n4 = 1.045321e+00 n5 = 1.045321e+00 v1#branch = -50.0000e-06 v2#branch = -50.0000e-06 vp = 1.30 (v2#branch/v1#branch) = 0.9999
And our relevant transistor' device parameters at the DC OP (re-formatted for display)
device m4 m3 m2 m1 model pmos pmos pmos pmos gm 959.282 uS 959.282 uS 620.8 uS 620.8 uS rds 93.017 kR 93.018 kR 199.14 kR 199.14 kR id 50 uA 50 uA 50 uA 50 uA vgs 0.3987 V 0.3987 V 0.4533 V 0.4533 V vds 0.1987 V 0.1987 V 0.2547 V 0.2547 V vth 0.3895 V 0.3895 V 0.3370 V 0.3370 V vdsat 0.0804 V 0.0804 V 0.1411 V 0.1411 V
DC Analysis (Sweep)[edit]
For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 1.3V to 0V in 0.05V increments.
We are plotting the output current magnitude vs drain voltage.
Monte Carlo Analysis[edit]
In our Montecarlo analysis, we are measuring the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistor parameters when added together can affect the performance of the overall circuit (please refer to the NMOS counterpart article for additional setup details for this simulation).
Results[edit]
For the cascoded current mirror, we can make the following observations
- The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.141 + 0.080 >> 0.221
- However as shown with the current sizing, the mirror output can go up to maximum 0.9V (at least ~0.4 vload voltage relative to vp) to yield its maximum Rout. (seen from the plot above where the slope is linear).
- Error Measurement: We see a variation of 50.0197uA to 49.9958uA over a linear operating vload range of 0 to 0.9V. This is equivalent to an error of 24nA or 0.05% relative to our reference.
Figures of Merit[edit]
Output Resistance Rout: 37.72MΩ (measured from 0.4 to 1.3V linear range).
Compliance Voltage Vmin: ~0.4V (from VP)
In summary,
| Topology | Vmin (V) | Compliance Voltage (V) | r_out (kΩ) | Current Consumption (uA) | Area (um^2) |
|---|---|---|---|---|---|
| Simple PMOS | 0.225 | 0.35 | 852.78 | 50 | 200 |
| PMOS Source Degenerated | 0.3536 | 0.45 | 2148 | 50 | 200 + 2 x A_res |
| PMOS 3T Res-biased Cascoded | 0.221 | 0.5 | 40000 | 50 | 1,358 + 1 x A_r8p73k |
| PMOS 4T Res-biased Cascoded | 0.221 | 0.4 | 37720 | 50 | 1,397 + 1 x A_r4k |
References[edit]
- Chapter 3 (pages 3-7)
Toolchain[edit]
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.
