NMOS 4T resistor-biased cascoded current mirror: Difference between revisions
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== Monte Carlo Analysis == |
== Monte Carlo Analysis == |
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[[File:NMOS_4T_resistor-biased_cascoded_current_mirror_simulation_mc_analysis.svg|800px]] |
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= Results = |
= Results = |
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Revision as of 02:15, 31 May 2023
Schematic Diagram
Circuit Netlist
* dev <nets> <values> * ----------------------------------- I1 n_pos n3 50uA V1 n_pos 0 1.3V V2 n2 0 0.5210533V R1 n3 n1 4.4kΩ M1 n4 n1 0 0 nmos W=20u L=3u M2 n5 n1 0 0 nmos W=20u L=3u M3 n2 n3 n5 0 nmos W=10u L=0.35u M4 n1 n3 n4 0 nmos W=10u L=0.35u
SPICE Simulations
Operating Point Analysis
Operating point DC measurement results (re-formatted for display):
n1 = 5.210533e-01 n2 = 5.210533e-01 n3 = 7.410507e-01 n4 = 2.673797e-01 n5 = 2.673795e-01 vp = 1.300000e+00 v1#branch = -50.00 uA v2#branch = -49.98 uA (v2#branch/v1#branch) = 0.9996
And our relevant transistor' device parameters at the DC OP (re-formatted for display)
device m4 m3 m2 m1 model nmos nmos nmos nmos gm 859.89 uS 859.89 uS 552.844 uS 552.844 uS gds 150.089 kR 150.089 kR 218.435 kR 218.435 kR id 49.979 uA 49.980 uA 49.984 uA 49.984 uA vgs 0.4737 V 0.4737 V 0.5210 V 0.5210 V vds 0.2537 V 0.2537 V 0.2674 V 0.2674 V vth 0.4536 V 0.4536 V 0.3880 V 0.3880 V vdsat 0.0787 V 0.0787 V 0.1471 V 0.1471 V
DC Analysis (Sweep)
File:NMOS 4T cascoded current mirror simulation dc analysis.svg
Monte Carlo Analysis
Results
Figures of Merit
References
- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-7)
Toolchain
- ICclopedia Toolchain.
- PTM 130nm CMOS SPICE models.
