Lateral PNP current mirror

The lateral PNP version can make use of a split collector for both collector branches as shown below. Given that a lateral-PNP is a poor bipolar device (doping and dimensions are not optimal), it's performance is inferior to that of the standard NPN mirror in a bipolar process, nevertheless it is an interesting alternative given that lateral PNP devices are sometimes made available in some CMOS processes.

In addition, one of the few advantages of lateral PNP transistors (see reference textbook below page 1-22) is that you can split the collector of the device into multiple sections and achieve excellent matching between collector currents (albeit at small currents only): thus the appropriate use of this device in a current mirror topology.

Schematic Diagram

Circuit Netlist

 * dev <nets>              <values>                                                                   
 * --------------------------------                                                                   
 I1    n1    0             50uA                                                                       
 V2    n2    0             4.288381V                                                                  
 V1    n_pos 0             5V                                                                         
 XQ1   n1    n2 n1 n_pos 0 split_coll_lat_pnp1  

SPICE Simulations

Operating Point Analysis

Calculating the DC voltages (bias voltages) at every node of our circuit.

Operating point DC measurement results (re-formatted for display):

n1 = 4.2884V
n2 = 4.2884V
n_pos = 5.0V
v1#branch = -99.021uA
v2#branch = 48.135uA
(v2#branch/50e-06) = 0.96271
                                                                                                                                                                                     

With a split collector lateral PNP transistor our nominal match is poorer than that shown in the Widlar NPN mirror, it has a larger static error from the 50uA reference.

DC Analysis (Sweep)

Measuring the variation of the mirrored output current under different loads.

We are applying a DC sweep to V2 (our load voltage) from 0 to 5V in 0.1V increments and plotting the output current magnitude vs collector voltage (our load voltage at n2). As can bee seen the current matching has degraded given finite Rout of the output transistor.

Results

In the circuit above, Q1 is the split-collector lateral PNP transistor. I1 biases the transistor and establishes a “diode” voltage drop from emitter to base (V_eb), the emitter current is then divided “identically” into two branches. (due to the split collector layout). However, there are two errors:

• There is a large collector current variation with changes in collector voltage (due to the early effect), moreover the effect is more pronounced for the lateral PNP current mirror than it was for the Widlar current mirror, mainly:

Error measurement: Variation of 53.5uA to 47.5uA over current mirror operating region (below 4.7V collector voltage). This is equivalent to an error of 6uA or 12% relative to our current reference.

• The second error (due to the use of a lateral PNP transistor) has to do with substrate currents (There is a competing PNP transistor: emitter, base, substrate). During normal operation a current about half the base current flows from emitter to substrate and under saturation the current increases to be almost the same as that of the collector.

In the graph above, this happens at a collector voltage of 4.7V or about 0.3V from the 5V positive supply.

Figures of Merit

Output Resistance Rout: 783.3kΩ (measured from 0 to 4.7V linear range).

Compliance Voltage Vmin: 0.3V (from positive supply)

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (page 3-2)

• Project files.

Toolchain

• ICclopedia toolchain.

• Bipolar process SPICE models