Lateral PNP Wilson current mirror

From ICclopedia

Schematic Diagram[edit]

Circuit Netlist[edit]

* dev <nets>               <values>                                                                  
* ---------------------------------                                                                  
V1    n_pos 0              5V                                                                        
I1    n3    0              50uA                                                                      
XQ1   n1    n3 n1  n_pos 0 split_coll_lat_pnp1                                                       
XQ2   n2    n3 n1  0       lat_pnp1                                                                  
V2    n2    0              4V 

SPICE Simulations[edit]

Walking through our simulation results we have:

Operating Point Analysis[edit]

Operating point DC measurement results (re-formatted for display):

n1 = 4.2884 V
n2 = 4.0 V
n3 = 3.5763 V
n_pos = 5.0 V
v1#branch = -99.936 uA
v2#branch = 48.083 uA
(v2#branch/50e-06) = 0.96167

Similar as before for the Wilson current mirror NPN, there is a static error due to the differing voltages for both current source and mirror branch collectors.

DC Analysis (Sweep)[edit]

In our DC analysis, we are measuring the variation of the mirrored output current under different loads.

We are applying a DC sweep to V2 (our load voltage) from 0 to 5V in 0.1V increments and plotting the output current magnitude vs collector voltage. (our load voltage at n2)


Note we are using lateral PNP models for both Q1 and Q2.

As shown above, there is a PNP equivalent circuit for the Wilson current mirror, it uses a split collector simple current mirror (Q1) to start, and adds an extra PNP transistor (Q2) to complete the the cascode stage and shield the collector of Q1 from load voltage fluctuations.

For the Wilson current mirror in the reference textbook, the following are the error measurements:

  • Variation of 48.17uA to 48.54uA over an operating range of 3.9V to 0V. This is equivalent to an error of 0.74% relative to the current reference.
  • The minimum voltage of the load (the voltage compliance) is given by the need to maintain a V_eb voltage for Q1 plus an (emitter to collector) effective voltage for Q2 to keep it in active.

Figures of Merit[edit]

  • Output Resistance: 10.54MR (from 3.9 to 0V linear range)
  • Compliance Voltage: 3.9V (from Vcc positive supply)