# Four transistor NPN Wilson current mirror

# Schematic Diagram[edit]

# SPICE Simulations[edit]

Walking through our simulation results we have:

## Operating Point Analysis[edit]

Calculating the operating point DC voltages and currents for our mirror, for a 1V output load.

Operating point DC measurement results (re-formatted for display):

n1 = 6.657271e-01 n2 = 1.331681e+00 n3 = 1.331681e+00 n4 = 6.661818e-01 n_pos = 5.000000e+00 v1#branch = -5.00000e-05 v2#branch = -4.99926e-05 (v2#branch/v1#branch) = 9.998513e-01

And the relevant transistors' device parameters at the DC OP:

model xq1:qn1_npn1 ic 4.95806e-05 ib 2.66706e-07 ie -4.98473e-05 vbe 0.664665 vbc 0.00260856 gm 0.00190188 gpi 1.01252e-05 go 9.13082e-07

model xq2:qn1_npn1 ic 4.95802e-05 ib 2.66706e-07 ie -4.98469e-05 vbe 0.664665 vbc 0.00306329 gm 0.00190186 gpi 1.01252e-05 go 9.13082e-07

model xq3:qn1_npn1 ic 4.99972e-05 ib 2.68925e-07 ie -5.02661e-05 vbe 0.664883 vbc 0.00308909 gm 0.00191781 gpi 1.02099e-05 go 9.20794e-07

model xq4:qn1_npn1 ic 4.91656e-05 ib 2.645e-07 ie -4.94301e-05 vbe 0.664446 vbc 0.00303775 gm 0.00188601 gpi 1.0041e-05 go 9.05416e-07

Now with symmetrical voltages at both branches (current source and mirror collectors), we have better matching than the NPN Wilson current mirror

## DC Analysis (Sweep)[edit]

In our DC analysis, we are measuring the variation of the mirrored output current under different loads.

We are applying a DC sweep to V2 (our load voltage) from 0 to 5V in 0.1V increments and plotting the output current magnitude vs collector voltage. (our load voltage at n2)

## Monte Carlo Analysis[edit]

Given that we now have more devices for our current mirror, the reference book emphasizes the importance of a Monte Carlo simulation to measure the effect of transistors’ mismatch on the performance of our current mirror i.e. how small variations in individual transistors when added together can affect the performance of the overall circuit.

Performing a Monte Carlo (mismatch) simulation on NGSPICE turned out to be difficult but possible with some effort.

The Monte Carlo Testbench SPICE source code provided below has been thoroughly commented to ease understanding. I have also added helpful references at the bottom of this post, and a “montecarlo_examples” directory in the repository.

The main thing to keep in mind in simulating device mismatches is that **the transistor model with its respective parameters needs to be placed inside a SPICE subcircuit**. This is the only way to be able to modify parameters independently for every transistor in the netlist, otherwise a change in model parameters propagates to all transistors.

The Monte Carlo simulation was performed for 100 runs with a sigma value of 3.

As per the book reference (in the simulation chapter) for bipolar transistors: independent variations of Is, Bf and the junction capacitances were simulated for each transistor.

# Results[edit]

As mentioned before for the NPN Wilson current mirror, there was a matching error for transistors Q1 and Q2: their collector voltages were not the same.

Thus a fourth transistor (Q4) was added, its main job to decrease the voltage at n3 by one V_be in order to bring the voltages n4 and n1 (the collector voltages for the current matching transistors Q1 and Q2) more closely in line.

The results as we can see from our Operating Point Analysis (v2#branch/v1#branch) is that we now have a 99.96% current match given a 1V load which is quite remarkable.

But indeed as mentioned in the reference book, variations due to transistors mismatch can account for as much as +2% to -5.6% (from our montecarlo simulation) relative to our reference current value.

*This error is larger than that of the book, unfortunately we don’t have the exact values used for the Montecarlo (mismatch) simulation in the book, nor the actual SPICE device parameters modified for every transistor during the simulation (this makes it almost impossible to compare results). However we will keep these results updated if any error is found.*

For the “Four Transistor” current mirror in the reference textbook, the following are the error measurements:

- Variation of 49.9797uA to 50.0468uA over an operating range of 1V to 5V. This is equivalent to an error of 0.1342% relative to the current reference.

- The minimum voltage of the load (the voltage compliance) is given by the need to maintain a V_be voltage for Q2 plus a (collector to emitter) effective voltage for Q3 (see figures of merit below).

## Figures of Merit[edit]

**Output Resistance:**59.61MR (from 1 to 5V linear range)

**Compliance Voltage:**1V (from ground)

# References[edit]

- Designing Analog Chips (Hans Camenzind)
- Chapter 3 (pages 3-5)

# Toolchain[edit]

- ICclopedia toolchain.

- Bipolar process NPN SPICE models