NMOS diode-biased cascoded current mirror

As compared to the canonical resistor-biased cascoded mirror, the use of a thin-diode to bias our cascode allows us to make do without any resistors and hence minimize area. However, the use of a thin-diode in place of a resistor-bias does come at the expense of an additional current branch and also a larger variation of the cascode bias over PVT and montecarlo. Hence in summary, with a diode-biased cascoded current mirror typically you can attain lower area at the cost of performance and larger a current consumption (although it really depends on the specific application).

The W/L ratio of the thin diode-connected device (M5) is chosen to yield the necessary cascode bias in order to equalize the drain voltages of M1 and M2 for best current match (as was done in the case of the NMOS 3T resistor-biased cascoded current mirror).

For many low-supply/headroom applications, the diode-biased topology can be a good choice to attain reduced area -- where a bias resistor may otherwise prove too large.

As before our cascoded rout is approximately given by:

r_out = ro2 x a3 = ro2 x (gm3 x ro3)

Note: the bias current I2 (used for the thin diode to generate the cascode bias) is typically just a mirrored version of the main bias current I1.

Schematic Diagram

Circuit Netlist

* dev <nets>      <values>                                                                                                                                                                
* -----------------------------------                                                                
I1    vp n1       50uA                                                                                                                                                                    
I2    vp n5       50uA                                                                                                                                                                    
V1    vp 0        1.3V                                                                               
V2    n2 0        0.5210616V                                                                                                                                                              
M1    n3 n1 0  0  nmos W=20u L=3u                                                                    
M2    n4 n1 0  0  nmos W=20u L=3u                                                                    
M3    n2 n5 n4 0  nmos W=10u L=0.35u                                                                                                                                                      
M4    n1 n5 n3 0  nmos W=10u L=0.35u                                                                                                                                                      
M5    n5 n5 0  0  nmos W=4u L=3u      

SPICE Simulations

Operating Point Analysis

Operating point DC measurement results (re-formatted for display):

n1 = 0.521
n2 = 0.521
n3 = 0.267
n4 = 0.267
n5 = 0.740
vp = 1.3 
v1#branch =  I1 + I2  =  (-50u) + (-50u)  
v1#branch = -100uA
v2#branch = -49.98uA
(v2#branch/50uA) = 0.9996

And our relevant transistor' device parameters at the DC OP (re-formatted for display)

device m5          m4           m3          m2          m1                                
model  nmos        nmos         nmos        nmos        nmos                              
gm     240.279 uS  859.945  uS  859.945 uS  552.793 uS  552.793 uS                        
gds    1.261   MR  150.73   kR  150.73  kR  215.65  kR  215.65  kR                        
id     49.989  uA  49.980   uA  49.980  uA  49.985  uA  49.985  uA                        
vgs    0.740   V   0.473    V   0.473   V   0.521   V   0.521   V                         
vds    0.740   V   0.255    V   0.255   V   0.266   V   0.266   V                         
vth    0.388   V   0.453    V   0.453   V   0.388   V   0.388   V                         
vdsat  0.310   V   0.079    V   0.079   V   0.147   V   0.147   V    

As seen given our cascode bias and sizing, we attain equal Vds for both source (m1) and mirror transistors (m2) and hence both branches are matched in performance.

DC Analysis (Sweep)

For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)

Monte Carlo Analysis

In our Montecarlo analysis, we are measuring the effect of transistors’ random mismatch on the output current of our mirror (i.e. how small random variations in individual transistor parameters when added together can result in an overall output current error).

Further details concerning Montecarlo simulation settings have been described under the NMOS 3T resistor-biased cascoded current mirror article and also apply here.

Results

For the cascoded current mirror, we can make the following observations

• The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.147 + 0.079 >> 0.226

• However as shown with the current sizing, the mirror requires at least ~0.4 load voltage to yield its maximum Rout. (seen from the plot above where the slope is linear).

• Error Measurement: We see a variation of 49.97326uA to 49.99395uA over a performance operating range of 0.4 to 1.3V. (keep in mind this is only for the typical corner, the real performance variation should be assessed over PVT where the cascode bias variation can be measured).

Figures of Merit

Output Resistance Rout: 43.50MΩ (measured from 0.4 to 1.3V linear range).

Compliance Voltage Vmin: ~0.4V (from ground)

In summary,

Current Mirrors Performance Summary

Topology	Vmin (V)	Compliance Voltage (V)	r_out (kΩ)	Bias Current (uA)	Area (um^2)
Simple NMOS	0.226	0.35	869.17	50	20
NMOS Source Degenerated	0.3815	0.45	1521	50	20 + 2 x A_r3k
NMOS 3T Res-biased Cascoded	0.221	0.5	18911	50	123.5 + 1 x A_r10p7k
NMOS 4T Res-biased Cascoded	0.226	0.4	43605	50	127 + 1 x A_r4p4k
NMOS Diode-biased Cascoded	0.226	0.4	43500	100	139

Please keep in mind, the area figures for the diode-biased cascoded example above are not considering the area of devices needed to mirror the I1 to I2 current

References

• Designing Analog Chips (Hans Camenzind)
  • Chapter 3 (pages 3-8)

• Project files.

Toolchain

• ICclopedia Toolchain.

• PTM 130nm CMOS SPICE models.