NPN emitter degenerated current mirror

= Schematic Diagram =



= Circuit Netlist =

* dev * --                                                                     V1    n_pos 0         5V I1   n_pos n1        50uA XQ1  n1    n1 n3 0   npn1 XQ2  n2    n1 n4 0   npn1 V2   n2    0         0.9630230V R1   n3    0 6KR R2   n4    0 6KR

= SPICE Simulations =

Walking through our simulation results we have:

Operating Point Analysis
Nominally with matched output load voltage (matched Vce across output transistor), calculating the operating point DC voltages and currents for our mirror.

Operating point DC measurement results (re-formatted for display and analysis):

n1 = 0.96302 V n2 = 0.96302 V n3 = 0.29752 V n4 = 0.29752 V n_pos = 5.0 V v1#branch = -50.0 uA v2#branch = -49.173 uA (v2#branch/v1#branch) = 0.98346

And our relevant transistors' device parameters at the DC OP (re-formatted for display and analysis):

device     q.xq1.q1  model      qn1_npn1 ic    49.177 uA     ib    0.26456 uA     ie    -49.441 uA    vbe     0.66445 V    vbc     3.0382 mV     gm     1.8864 mS    rpi     99.569 kR     ro     1.1042 MR

device     q.xq2.q1  model      qn1_npn1 ic    49.174 uA     ib    0.26454 uA     ie    -49.438 uA    vbe     0.66445 V    vbc     3.0382 mV     gm     1.8863 mS    rpi     99.575 kR     ro    1.1043  MR

Here as before, because of the finite base current there is a small static error from the nominal reference 50uA current.

DC Analysis (Sweep)
In our DC analysis, we are measuring the variation of the mirrored output current under different loads.

We are applying a DC sweep to V2 (our load voltage) from 0 to 5V in 0.1V increments and plotting the output current magnitude vs collector voltage. (our load voltage at n2)

As can bee seen our current output over changing load has now improved compared to the simple BJT mirror presented before.



= Results =

From the circuit above we can see that as the emitter current increases, the voltage across R2 increases, this subsequently reduces the base emitter voltage (V_be) of Q2 which then acts to decrease the emitter current, next the voltage drop across R2 decreases and V_be increases, more current flows ...etc. and the process repeats itself until a set-point is reached and loop errors are reduced.

In principle for the circuit above, because the base voltage is fixed, the process repeats itself until the voltage drop across R2 (which is proportional to our output current) remains constant and equal to the voltage drop across R1 (our setpoint, which is proportional to our current reference), with any errors in R2’s voltage (due to collector voltage dependence) subtracted from our input (V_be).

In our reference book example, having 6KR emitter resistors acts to reduce the output current dependence on load voltage and increases the output resistance of the mirror (see “figures of merit” section below), more specifically:


 * Error Measurement: Variation of 49.13uA to 49.51uA over an operating range of 0.6 to 5V. This is equivalent to an error of 0.38uA or 0.76% relative to the current reference.

However, the extra resistors also increase the minimum collector voltage the mirror can operate at (the compliance voltage), as we now have to account for both the voltage drop across R2 in addition to the voltage across Q2 in saturation. Furthermore, there is the case of the base current error which has not been resolved either.

Note that we can also use resistors for negative feedback in MOS current mirrors by placing the resistors in the sources of both transistors, as shown in MOS current mirrors with source degeneration resistors.

Figures of Merit
Output Resistance Rout: 11.58 MR (from 0.6 to 5V range).

Compliance Voltage Vmin: 0.6 V (from ground)

= References =


 * Designing Analog Chips (Hans Camenzind)
 * Chapter 3 (pages 3-3)


 * Project files.

= Toolchain =


 * ICclopedia toolchain.


 * Bipolar process NPN SPICE models