NMOS characterization (PTM 130)

The characterization testbench schematic for a nominal NMOS transistor in technology is displayed below:

= Schematic diagram = General transistor characterization testbench.



= SPICE simulations =

DC analysis (sweep): Large signal parameters
We will be plotting the normalized transistor large-signal I/V transfer curves.

Id vs Vds for different Vgs bias
Here we are sweeping Vds from 0 to 1.3V in 0.05 increments, and subsequently incrementing Vgs from 0.1 to 1.3 in 0.1 increments.

For the I/V characterization curves, a minimum transistor length of L=130nm was used together with a total width of 10um (Wf=1um, Nf=10, m=1).



The following are the simulated Vdsat values for each Vgs curve for reference (these are evaluated at Vds=Vdd bias conditions):

Vgs: At Vgs: 0.1 V, Vdsat: 0.0390523 Vgs: At Vgs: 0.2 V, Vdsat: 0.0429505 Vgs: At Vgs: 0.3 V, Vdsat: 0.0604041 Vgs: At Vgs: 0.4 V, Vdsat: 0.0947588 Vgs: At Vgs: 0.5 V, Vdsat: 0.134929 Vgs: At Vgs: 0.6 V, Vdsat: 0.174607 Vgs: At Vgs: 0.7 V, Vdsat: 0.213001 Vgs: At Vgs: 0.8 V, Vdsat: 0.250484 Vgs: At Vgs: 0.9 V, Vdsat: 0.287404 Vgs: At Vgs: 1.0 V, Vdsat: 0.323967 Vgs: At Vgs: 1.1 V, Vdsat: 0.360294 Vgs: At Vgs: 1.2 V, Vdsat: 0.396457 Vgs: At Vgs: 1.3 V, Vdsat: 0.4325

The Vdsat delimits the operating region of this transistor. For Vds < Vdsat the device is in the triode region of operation, for Vds > Vdsat the device is in the saturation region of operation.

Looking at each operating region, A couple of helpful insights can be provided given our DC transfer curves above.

Saturation Region
The maximum current density is attained in deep saturation (maximum Vds) and strong inversion (maximum Vgs). For our NMOS device approaches the traditional "rule of thumb" max figure of 1mA/μm; this is always helpful as a sanity check.

Keep in mind as well, if we want to bias the device at a different inversion level (e.g. weak inversion), these DC transfer curves are useful to understand the maximum attainable current density under those bias conditions; and hence the minimum device width required for the desired bias current.

Also, in designing an amplifier where a large output swing is expected at the output, we often want to set the Vds bias voltage at the mid-point between our supply and the min vdsat for the desired gate-source bias voltage and operating region: this will help us yield the largest swing while maintaining the transistor in saturation. We can do this graphically and more intuitively using a load line analysis.

Triode Region
If we instead are looking into the design of switches, we can make use of these transfer curves to get a good idea for the Ron (ON resistance) or alternatively the Gon (ON conductance) we can expect for the transistor device in triode over a range of vds voltages across; recall triode devices experience non-linear resistance.

For example take a 1μm wide device, the minimum Ron given a 1.3V gate drive would be drain to source voltage by the current across it, roughly 0.4v/0.8ma at the edge of sat to 0.1V/0.3mA in deep triode; or around 500 to 300 Ω.

But given we know the current density, a more useful width-scalable metric would be its conductance density (i.e. the current density by the voltage across it) as shown below: $$G_{density} = \frac{j}{V_{ds}}$$ In units of $$\frac{mA}{μm \times V}$$

Hence for a standard minimum length switch device, sometimes if you know the DC voltage across the switch plus necessary Gon, we can conveniently calculate the necessary width.

Although note in the design of switches we should also understand the parasitics which would set not-only the RC corner frequency/bandwidth of the switch but also the gate-drive requirements. (i.e. if we opt for a very wide switch with low Ron we pay a price in drive power for certain and could pay a price in bandwidth depending on the RC of the switch.)

Id vs Vgs for different Vbs (back-gate) bias


The following shows the increasing device threshold voltage (measured at Vgs=Vdd) with increasing bulk to source bias; or conversely the more common case: increasing threshold voltage with increasing source to bulk bias (recall often the bulk is at the common lowest potential for NMOS devices unless it is placed in it's own well).

At Vbs: 0.0 V, Vth: 0.300577 At Vbs: -0.1 V, Vth: 0.326095 At Vbs: -0.2 V, Vth: 0.350393 At Vbs: -0.3 V, Vth: 0.373635 At Vbs: -0.4 V, Vth: 0.395952 At Vbs: -0.5 V, Vth: 0.41745 At Vbs: -0.6 V, Vth: 0.438215 At Vbs: -0.7 V, Vth: 0.458321 At Vbs: -0.8 V, Vth: 0.477828 At Vbs: -0.9 V, Vth: 0.496789 At Vbs: -1.0 V, Vth: 0.51525 At Vbs: -1.1 V, Vth: 0.533249 At Vbs: -1.2 V, Vth: 0.550821 At Vbs: -1.3 V, Vth: 0.567996

This Vbs (or Vsb) bias, either applied by design or as a result of the topology employed (e.g. where the source is not at the lowest bulk potential) can result in modulation of the device threshold voltage, or can also be seen in a different way as a "back gate" (given a fixed Vgs bias) -- although with a lower transconductance.

Looking at each operating region, A couple of interesting effects can arise as a result of this back-gate bias (more often than not in ways that are detrimental to the circuit performance).

Saturation Region
In biasing a device in saturation, one must be aware of the impact a back-gate bias has on Vth, Vgs and the Vdsat of the device.

In most cases, with the increases in source voltage, Vgs decreases proportionally (assuming fixed bias gate voltage), what this means is given Vdsat = Vgs - Vth (to a first order), with decreasing Vgs and increasing Vth our Vdsat decreases and for the same bias conditions, the device is further in saturation; this may alter our desired operating point. Hence one should take care to consider the effect on Vth, the actual Vgs, and resulting Vdsat when biasing the amplifier in sat region.

Another perhaps more important effect of the increase in source voltage is the change in the inversion level of the device. Naturally, With the decrease in Vgs the device is placed into weaker inversion, moreover the simultaneous increase in Vth due to the body-effect, places the device into a further weaker inversion state. As both Vgs and Vth are changing inversely, if care is not taken to account for this, a device can even go into cutoff (where no inversion layer is effectively present).

We can see the body-effect first-hand in the plot above, for the same drain to source voltage, in order to attain the same current density given a lower Vbs bias (or equivalently a larger source-bulk voltage) we need to increase the device Vgs. The back-gate bias increases the threshold, effectively putting the device in weaker inversion: hence to reach the same original inversion state (and drain current) we need to increase the Vgs voltage.

Triode Region
In the case of the device biased in triode region, we can see that the back-gate much like the device's gate gives us some degree of non-linear resistance control; however, in most applications if a device in triode is employed, feedback is used to arrive at a desired resistance value (except in cases where the actual resistance value is not critical e.g. pull-up/down devices).

DC analysis (sweep): Design parameters vs. Veff (for various Vbs)
The transconductor nominal design parameters are plotted below for the reference minimum-length transistor with various back-gate Vbs.

Most important are the design parameter plots for Vbs=0V (i.e. with no back-gate voltage): These plots are most useful for starting choosing a Veff bias point to start a design.

gm/id: current efficiency


The gm/Id design parameter is extremely useful for designing power efficient circuits. This parameter, namely the transconductor current efficiency, tells you how much transconductance gain you can get per bias current spent. As can be seen above, there is a fundamental maximum value that can be attained governed by physical laws.

$$\frac{gm}{Id} <= \frac{1}{n U_T}$$

Where U_T is the thermal voltage (kT/q) and n is the device's sub-threshold slope factor.

In fact, as power efficiency is concerned, it will be shown there is a clear trade-off between power, area and speed.

gm/w: area efficiency


The transconductor area efficiency design parameter tells you at a particular overdrive bias point, what the width needs to be in order to meet a required gm.

For instance, if you opt to bias your device in weak inversion say in order to operate at high gm/id and hence spend little current for your necessary gm; invariably as can be seen on the left-hand side in the plot above, you will need to operate at low area efficiency therefore you will need to employ a large area (you are trading off area for low-power) to attain such gm.

On the other hand, if you'd like to reduce the area footprint by operating in strong inversion (at large gm/w) and choosing a small w to meet your necessary gm, you will need to operate in the low gm/id region and hence spend more power to yield the same gm (you are trading off power for low-area).

Ft: unity gain frequency


As is well known, in order to squeeze as much speed for your device, you need to operate in strong inversion where the Ft and hence bandwidth of your device is at it's maximum (keep in mind the plot above is in a logarithmic scale).

Hence we have the three fundamental tradeoff's that define your design choices based on your primary requirement:


 * If you need low-power operation (large gm/id via operation in weak inversion), this comes at the cost of large area (low gm/w) and reduced bandwidth. This is a good choice for DC amplifiers where all you care about is gain at DC and bandwidth is an afterthought.


 * If you need speed (large Ft via operation in strong inversion), this comes at the cost of higher power (low gm/Id), but area can be reduced as this grants operation in high gm/w: as should be expected given the need to reduce self-parasitics to meet high bandwidth. This is a good choice for RF integrated circuits.


 * If you need a small-area (large gm/w via operation on strong inversion), again you need to pay up power given operation at low gm/id; but correspondingly you can also take advantage of faster devices.

DC analysis (sweep): Design parameters vs. Veff (for various lengths)
Design parameters are plotted below for a set of transistors with lengths spanning from 130nm to 3um (roughly following technology nodes progression) to help compare trade-offs in choosing device dimensions (width chosen as before).

Noise Characterization
Another important thing to consider is noise introduced by the device itself, here again one must increase power if it is desired to reduce intrinsic noise. (this should be expanded further)


 * (currently just a placeholder) Need to expand this and correct from notes, also move out of here to include elsewhere, perhaps with tran noise sims in another section*

Recall fundamentally, if we look only at thermal noise (Major contributor at frequencies beyond 1/f knee in spectrum). $$P_n = 4 \times K \times T \times f_{bw}$$

Where the f_bw relates to the applicable noise bandwidth integrated over.

If then we consider thermal noise is due to brownian motion in conductive (resistive) elements, we can express:

$$\frac{V^2}{R} = 4 \times K \times T \times f_{bw}$$

Such that:

$$\frac{V^2}{R} = 4 \times K \times T \times f_{bw}$$

$$V^2 = 4 \times K \times T \times R \times f_{bw}$$

And we arrive at a common metric for effective noise voltage (volts square per hz or volts per root hz):

$$\frac{V^2}{Hz} = 4 \times K \times T \times R $$


 * Need to expand this and correct not right*

= References =


 * T. Chan Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design. 2nd edition, J. Wiley & Sons, 2011.


 * P. G. A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge: Cambridge University Press, 2017.

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.