NMOS current mirror

= Schematic Diagram =



= SPICE Simulations =

Walking through our simulation results we have:

Operating Point Analysis
Nominally with matched output load voltage (matched Vds across output transistor), calculating the operating point DC voltages and currents for our mirror.

Operating point DC measurement results (re-formatted for display):

n1 = 0.63027 n2 = 0.63027 n_pos = 1.3 v1#branch = -50.0 uA v2#branch = -49.989 uA (v2#branch/v1#branch) = 0.99977

And out relevant transistors' device parameters at the DC OP (re-formatted for display):

device           m2            m1  model          nmos          nmos gm   347.132 uS    347.132 uS    rds     920.43 kR     920.43 kR     id     49.991 uA     49.991 uA    vgs     0.63026 V     0.63026 V    vds     0.63026 V     0.63026 V    vth     0.38804 V     0.38804 V  vdsat     0.22641 V     0.22641 V

As seen given our equal Vds for both source and mirror transistors, both branches are very well matched in performance.

DC Analysis (Sweep)
However, in a real life scenario our load could vary widely hence degrading our current match. For this purpose, in our DC analysis, we are measuring the variation of the mirrored output current under different applied loads.

We are applying a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments and plotting the output current magnitude vs drain voltage. (our load voltage at n2)



As can bee seen our current matching has degraded given finite Rout of the output transistor.

= Results =

For the Simple NMOS Current Mirror:


 * The absolute minimum voltage needed for the mirror to be in the saturation region is its Vdsat (roughly a Veff) at the nominal 50uA mirror current i.e:


 * Vmin_abs = Vdsat = 0.22641V


 * However in practice the current mirror requires at least a 0.35V load voltage to be operational with the maximum Rout (this can be seen from the plot above). Note lower compliance voltages may be achieved through the use of larger devices.


 * The variation of the drain current with changes in load voltage is as follows:


 * Error Measurement: Variation of 49.473uA to 50.566uA over an operating range of 0.35 to 1.3V. This is equivalent to an error of 1.093uA or 2.186% relative to our current reference.


 * Note that this topology is symmetrical and can be inverted by using PMOS transistors connected to the positive supply rail instead, as shown in the PMOS mirror in subsequent sections.

Figures of Merit
Output Resistance Rout: 869.17kΩ (measured from 0.35 to 1.3V linear range). Note this is roughly consistent with our device output resistance (rds) parameter seen above.

Compliance Voltage Vmin: 0.35V (from ground)

= References =


 * Designing Analog Chips (Hans Camenzind)
 * Chapter 3 (page 3-3)


 * Project files.

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.