NMOS self-biased cascoded current mirror

In this topology we can forgo the need to use an additional thin diode to generate our cascode bias. Instead we can make use of the input branch bias voltage and place a cascode in-between with its vgs setting the vds of our bias and mirror devices. This topology also has the benefit of being fully symmetrical being advantageous in reducing any systematic offset that may arise otherwise.

The simplicity of this topology comes at a cost however: to be able to re-use the input branch diode voltage as a cascode bias, we need to make the input diode W/L thinner to raise this bias, in addition we need to make use of a wide cascode to reduce the vgs across it and allow enough sat margin for the bias and mirror devices. While this topology can be useful in many application the above shortcomings can sometimes over-constrain the design choices and result in either an impractically large area for the cascode or insufficient sat margin for the mirror (to allow it to be on the performance range of the r_out curve).

In progress

= Schematic Diagram =



= Circuit Netlist = * dev * ---                                                                I1    vp n1      50uA V1   vp 0       1.3V V2   n2 0       0.5957451V M1   n3 n1 0 0  nmos W=10u  L=3u M2   n4 n1 0 0  nmos W=10u  L=3u M3   n2 n1 n4 0 nmos W=100u L=0.35u M4   n1 n1 n3 0 nmos W=100u L=0.35u

= SPICE Simulations =

Operating Point Analysis
Operating point DC measurement results (re-formatted for display): n1 = 5.957451e-01 n2 = 5.957451e-01 n3 = 2.433388e-01 n4 = 2.433388e-01 v1#branch = -5.00000e-05 v2#branch = -4.99751e-05 vp = 1.300000e+00 (v2#branch/v1#branch) = 9.995028e-01

And our relevant transistor' device parameters at the DC OP (re-formatted for display) device                   m4                    m3                    m2      model                  nmos                  nmos                  nmos gm           0.00111967            0.00111967           0.000389696 gmbs          0.000275255           0.000275255           0.000112598 gds          5.79305e-06           5.79305e-06           1.77968e-05 id          4.99752e-05           4.99752e-05           4.99812e-05 vgs             0.352406              0.352406              0.595745 vds             0.352406              0.352406              0.243339 vbs            -0.243339             -0.243339           4.88245e-13 vth             0.447807              0.447807              0.388024 vdsat            0.0477548             0.0477548              0.201722

BSIM4v5: Berkeley Short Channel IGFET Model-4 device                   m1      model                  nmos gm          0.000389696 gmbs          0.000112598 gds          1.77968e-05 id          4.99812e-05 vgs             0.595745 vds             0.243339 vbs          4.88245e-13 vth             0.388024 vdsat             0.201722

Monte Carlo Analysis


= Results =

Figures of Merit
= References =

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.