NPN current mirror

= Schematic Diagram =



= Circuit Netlist = * Circuit Elements: Devices * dev * --                                                                     V1    n_pos 0         5V I1   n_pos n1        50uA XQ1  n1    n1 0 0    npn1 XQ2  n2    n1 0 0    npn1 V2   n2    0         0.6655033V

= SPICE Simulations =

Walking through our simulation results we have:

Operating Point Analysis
Nominally with matched output load voltage (matched Vce across output transistor), calculating the operating point DC voltages and currents for our mirror.

Operating point DC measurement results (re-formatted for display):

n1 = 0.66550 n2 = 0.66550 n_pos = 5.0 v1#branch = -50.0uA v2#branch = -49.172uA (v2#branch/v1#branch) = 0.98345

And our relevant transistors' device parameters at the DC OP (re-formatted for display and analysis):

device     q.xq1.q1  model      qn1_npn1 ic    49.173 uA     ib    0.26454 uA     ie    -49.437 uA    vbe     0.66445 V    vbc     3.0382 mV     gm     1.8863 mS    rpi     99.577 kR     ro     1.1043 MR device      q.xq2.q1  model      qn1_npn1 ic    49.173 uA     ib    0.26454 uA     ie    -49.437 uA    vbe     0.66445 V    vbc     3.0382 mV     gm     1.8863 mS    rpi     99.577 kR     ro     1.1043 MR

Given our equal Vce for both source and mirror transistors, both branches are very well matched in performance. However, because of the finite base current there is a static error from the nominal reference 50uA current.

DC Analysis (Sweep)
In our DC analysis, we are measuring the variation of the mirrored output current under different loads.

We are applying a DC sweep to V2 (our load voltage) from 0 to 5V in 0.1V increments.

We are plotting the output current magnitude vs collector voltage. (our load voltage at n2)



As can bee seen our current matching has degraded given finite Rout of the output transistor.

= Results =

From our operating point analysis we can see both transistors are operating in the active region as expected (BE junction forward biased, BC junction reverse biased).

Additionally, given our diode-connected (collector-base-tied transistor) Q1 and our bias current I1, we should see a “diode” voltage drop from collector-base to emitter (Vbe). Thus, because Q1 and Q2 share the same base-emitter voltage, therefore the collector current of Q2 should match identically that of Q1, except for two errors:


 * From our simulation results above with our 0.66V matched load, we can see that currents v1#branch and v2#branch are very close, but not exactly identical, there is a static error. (and it gets worse as soon as we “introduce” a load)


 * The reason for this has to do with the base currents of both Q1 and Q2.


 * Given a current gain (or beta = i_collector/i_base) of roughly 100, we can expect 1% of I1 to go to the base of Q1 and 1% to go to the base of Q2, for the worst case.


 * Error (worst case): 1.655% relative to the current source reference, or 0.828uA in our case.


 * The early effect degrades the current matching performance of Q2 under different loads.


 * While the collector voltage of Q1 remains fixed at V_be, the collector voltage of Q2 can change: Our load voltage can be anything. Now, due to the early effect for bipolar transistors, as the collector voltage increases, the collector current also increases and no longer matches that of I1.


 * This means our current mirror does not accurately match the source current under different loads; We can see the extent of this error in our DC analysis plot.


 * Error measurement: Variation of 48.8uA to 53uA over current mirror operating region (roughly above 0.3V collector voltage). This is equivalent to an error of 4.2uA or 8.4% relative to our current reference.

There are ways to compensate for these errors through the use of additional transistors as can be seen in our directory of current mirrors.

Figures of Merit
Output Resistance Rout: 1.12MΩ (from 0.3 to 5V range). Note this is roughly consistent with our device output resistance (ro) parameter seen above.

R_out = (5V - 0.3V) / (53uA - 48.8uA) R_out = 1.12 MR

Compliance Voltage Vmin: 0.3 V (from ground)

= References =


 * Designing Analog Chips (Hans Camenzind)
 * Chapter 3 (pages 3-1 and 3-2)


 * Project files.

= Toolchain =


 * ICclopedia toolchain.


 * Bipolar process SPICE models