PMOS characterization (PTM130)

Characterization testbench schematic for a nominal PMOS transistor in the technology. This procedure is complementary to the NMOS characterization PTM 130 and follows in a similar fashion.

= Schematic diagram = General transistor characterization testbench.



= SPICE simulations =

To characterize the PMOS transistor we'd like to perform three DC simulation sweeps, outlined in the next sections.

Note: as for the NMOS characterization, for the last two analyses note the dashed line indicates the point where Veff=0 (Vgs=Vth) and the transistor transitions from weak (sub-threshold) to moderate inversion operation.

DC analysis (sweep): Large signal parameters
Here we are plotting the normalized transistor large-signal I/V transfer curves.

Id vs Vds for different Vgs bias
We are sweeping Vds from 0 to 1.3V in 0.05 increments, and subsequently decreasing Vgs from -0.1 to -1.3 in -0.1 increments.

For the I/V characterization curves, a minimum transistor length of L=130nm was used together with a total width of 10um (Wf=1um, Nf=1, m=1).



The following are the simulated Vdsat values for each Vgs curve for reference:

Vgs: At Vgs: -0.1 V, Vdsat(@Vds=-Vdd): -0.0482195 Vgs: At Vgs: -0.2 V, Vdsat(@Vds=-Vdd): -0.0641427 Vgs: At Vgs: -0.3 V, Vdsat(@Vds=-Vdd): -0.110054 Vgs: At Vgs: -0.4 V, Vdsat(@Vds=-Vdd): -0.176295 Vgs: At Vgs: -0.5 V, Vdsat(@Vds=-Vdd): -0.245127 Vgs: At Vgs: -0.6 V, Vdsat(@Vds=-Vdd): -0.311269 Vgs: At Vgs: -0.7 V, Vdsat(@Vds=-Vdd): -0.374742 Vgs: At Vgs: -0.8 V, Vdsat(@Vds=-Vdd): -0.436258 Vgs: At Vgs: -0.9 V, Vdsat(@Vds=-Vdd): -0.496378 Vgs: At Vgs: -1.0 V, Vdsat(@Vds=-Vdd): -0.555485 Vgs: At Vgs: -1.1 V, Vdsat(@Vds=-Vdd): -0.613852 Vgs: At Vgs: -1.2 V, Vdsat(@Vds=-Vdd): -0.671675 Vgs: At Vgs: -1.3 V, Vdsat(@Vds=-Vdd): -0.729101

Id vs Vgs for different Vbs (back-gate) bias


At Vbs: 0 V, Vth(@Vgs=Vdd): -0.232326 At Vbs: 0.1 V, Vth(@Vgs=Vdd): -0.253784 At Vbs: 0.2 V, Vth(@Vgs=Vdd): -0.274114 At Vbs: 0.3 V, Vth(@Vgs=Vdd): -0.293468 At Vbs: 0.4 V, Vth(@Vgs=Vdd): -0.311969 At Vbs: 0.5 V, Vth(@Vgs=Vdd): -0.329714 At Vbs: 0.6 V, Vth(@Vgs=Vdd): -0.346783 At Vbs: 0.7 V, Vth(@Vgs=Vdd): -0.363245 At Vbs: 0.8 V, Vth(@Vgs=Vdd): -0.379156 At Vbs: 0.9 V, Vth(@Vgs=Vdd): -0.394564 At Vbs: 1.0 V, Vth(@Vgs=Vdd): -0.409512 At Vbs: 1.1 V, Vth(@Vgs=Vdd): -0.424034 At Vbs: 1.2 V, Vth(@Vgs=Vdd): -0.438164 At Vbs: 1.3 V, Vth(@Vgs=Vdd): -0.451929

DC analysis (sweep): Design parameters vs. Veff (for various Vbs)
Nominal design parameters are plotted below for the reference minimum-length transistor with various back-gate Vbs.

Most important are the design parameter plots for Vbs=0V (i.e. with no back-gate voltage): These plots are most useful for starting choosing a Veff bias point to start a design. As before, in cases where the source is not at the same potential as the bulk, it is illustrative to see how design parameters change for the same applied Vgs i.e. due to the body effect.



DC analysis (sweep): Design parameters vs. Veff (for various lengths)
Design parameters are plotted below for a set of transistors with lengths spanning from 130nm to 3um (roughly following technology nodes progression) to help compare trade-offs in choosing device dimensions (width chosen as before).



= References =


 * T. Chan Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design. 2nd edition, J. Wiley & Sons, 2011.


 * P. G. A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge: Cambridge University Press, 2017.

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.