NPN Wilson current mirror

= Schematic Diagram =



= Circuit Netlist =

* dev * --                                                                     V1    n_pos 0         5V I1   n_pos n3        50uA XQ1  n3    n1 0  0   npn1 XQ2  n1    n1 0  0   npn1 XQ3  n2    n3 n1 0   npn1 V2   n2    0         1V

= SPICE Simulations =

Walking through our simulation results we have:

Operating Point Analysis
Calculating the operating point DC voltages and currents for our mirror, for a 1V output load.

Operating point DC measurement results (re-formatted for display):

n1 = 0.66541 V n2 = 1.0 V n3 = 1.3312 V n_pos = 5.0 V v1#branch = -50.0 uA v2#branch = -49.402 uA (v2#branch/v1#branch) = 0.98803

And the relevant transistors' device parameters at the DC OP:

device       q.xq1.q1  model        qn1_npn1 ic     4.9578e-05 ib    2.63493e-07 ie   -4.98414e-05 vbe       0.664346 vbc      -0.662731 gm     0.00190196 gpi    1.00028e-05 go    9.01937e-07

device       q.xq2.q1  model        qn1_npn1 ic    4.89989e-05 ib    2.63612e-07 ie   -4.92625e-05 vbe       0.664358 vbc     0.00302744 gm     0.00187964 gpi    1.00072e-05 go    9.02332e-07

device       q.xq3.q1  model        qn1_npn1 ic    4.94074e-05 ib    2.70837e-07 ie   -4.96783e-05 vbe       0.664735 vbc       0.334253 gm      0.0018953 gpi    1.01524e-05 go    9.20969e-07

While both branches are well matched in performance. Here, there is a static error due to the differing voltages for both the current source and mirror branch collectors.

DC Analysis (Sweep)
In our DC analysis, we are measuring the variation of the mirrored output current under different loads.

We are applying a DC sweep to V2 (our load voltage) from 0 to 5V in 0.1V increments and plotting the output current magnitude vs collector voltage. (our load voltage at n2)



= Results =

In this circuit the combination of the load, Q3 and Q2 form a cascode stage. This stage shields the simple current mirror (Q1 and Q2) from load voltage fluctuations but also introduces a negative feedback loop into the system.

Initially all transistors are OFF, shortly thereafter a small current starts to flow into the base of Q3 which starts to conduct, the emitter current of Q3 then biases the current mirror formed by Q1 and Q2. As Q1 starts to conduct (and given our constant current reference), it reduces the base current of Q3. In turn, Q3 emitter current decreases which leads to reductions in Q1 and Q2 collector currents, the reduction in Q1’s collector current makes more current available for the base of Q3 and the process repeats itself from the beginning until loop errors are reduced (i.e. subtracted from Q3 base current); a constant setpoint is reached when the load current matches closely the reference current. (see a detailed explanation of the circuit here)

Furthermore, it is worth noting that the base error previously found in the simple 2-transistor current mirror is minimized. I.e. while the base current for Q3 is still taken from the reference (1), it is amplified by the current gain of Q3 and a small fraction of Q3’s larger emitter current is fed-back to drive the bases of Q1 and Q2 (2). These effects compensate for each other, with the collector current of Q3 (the output current) greater than that of Q1 and more closely matched to our current reference.

For the Wilson current mirror in the reference textbook, the following are the error measurements:


 * Variation of 49.409uA to 49.467uA over an operating range of 1.1V to 5V.
 * This is equivalent to an error of 0.116% relative to the current reference.


 * The minimum voltage of the load (the voltage compliance) is given by the need to maintain a collector voltage for Q3 of: V_be for Q2, plus the effective (collector to emitter) voltage to keep Q3 in active (see figures of merit).


 * The current mirror transistors Q1 and Q2 are not perfectly matched: the collector voltage of Q1 is at 2V_be while that of Q2 is at V_be. This error will be explored and minimized in the improved Four transistor NPN Wilson current mirror topology.

The compliance voltage of this circuit is rather high which limits the use of this topology outside of the scope of most low power applications

There is also a simulation of a lateral PNP wilson current mirror.

Figures of Merit

 * Output Resistance: 67.24MR (from 1.1 to 5V linear range)


 * Compliance Voltage: 1.1V (from ground)

= References =


 * Designing Analog Chips (Hans Camenzind)
 * Chapter 3 (pages 3-4)


 * Project files.

= Toolchain =


 * ICclopedia toolchain.


 * Bipolar process NPN SPICE models