PMOS characterization (PTM130)

Characterization testbench schematic for a nominal PMOS transistor in the technology. This procedure is complementary to the NMOS characterization PTM 130 and follows in a similar fashion.

= Schematic diagram = General transistor characterization testbench.



= SPICE simulations =

To characterize the PMOS transistor we'd like to perform three DC simulation sweeps.


 * First, we will plot the normalized I/V transfer curves for the transistor for different applied Vgs bias voltages.


 * Second, the normalized Id current vs. Vgs gate-source voltage for different Vbs back-gate bias voltages.


 * Third, using the same reference minimum length transistor, we will plot all design parameters vs. Veff (as a proxy for inversion level).


 * Lastly, we want to inspect the variation in design parameters vs. Vgs for different length transistors.

As before, note the dashed line indicates the point where Veff=0 (Vgs=Vth) and the transistor transitions from weak (sub-threshold) to moderate inversion operation.

DC analysis (sweep): Large signal parameters
We will be plotting the normalized transistor large-signal I/V transfer curves.

Id vs Vds for different Vgs bias
Here we are sweeping Vds from 0 to 1.3V in 0.05 increments, and subsequently decreasing Vgs from -0.1 to -1.3 in -0.1 increments.

For the I/V characterization curves, a minimum transistor length of L=130nm was used together with a total width of 10um (Wf=1um, Nf=1, m=1).



The following are the simulated Vdsat values for each Vgs curve for reference:

Include sim results here

Id vs Vgs for different Vbs (back-gate) bias


Include sim results here

DC analysis (sweep): Design parameters vs. Veff (for various Vbs)
Nominal design parameters are plotted below for the reference minimum-length transistor with various back-gate Vbs.

Most important are the design parameter plots for Vbs=0V (i.e. with no back-gate voltage): These plots are most useful for starting choosing a Veff bias point to start a design. As before, in cases where the source is not at the same potential as the bulk, it is illustrative to see how design parameters change for the same applied Vgs i.e. due to the body effect.



DC analysis (sweep): Design parameters vs. Veff (for various lengths)
Design parameters are plotted below for a set of transistors with lengths spanning from 130nm to 3um (roughly following technology nodes progression) to help compare trade-offs in choosing device dimensions (width chosen as before).



= Results =

= References =

= Toolchain =