NMOS diode-biased cascoded current mirror

= Schematic Diagram =



= Circuit Netlist =

* dev * ---                                                                I1    vp n5         50uA I2   vp n3         50uA V1   vp 0          1.3V V2   n2 0          0.65V M1   n1 n1 0  0    nmos W=20u L=3u M2   n4 n1 0  0    nmos W=20u L=3u M3   n2 n3 n4 0    nmos W=10u L=0.35u M4   n5 n3 n1 0    nmos W=10u L=0.35u M5   n3 n3 0  0    nmos W=1.4u L=3u

= SPICE Simulations =

Operating Point Analysis
Operating point DC measurement results (re-formatted for display): n1 = 0.520 n2 = 0.650 n3 = 1.055 n4 = 0.520 vp = 1.3 v1#branch = I1 + I2  =  (-50u) + (-50u) v1#branch = -100uA v2#branch = -49.981uA (v2#branch/50uA) = 0.9996

And our relevant transistor' device parameters at the DC OP (re-formatted for display) device       m5           m4           m3           m2           m1                  model       nmos         nmos         nmos         nmos         nmos gm   117.497 uS   833.258 uS   836.715 uS   556.736 uS   556.733 uS                  gds     1.641 MR    23.994 kR    29.214 kR    874.72 kR    874.38 kR                   id     49.964 uA    50.000 uA    49.981 uA    49.986 uA    49.986 uA                   vgs     1.055  V      0.535 V      0.535 V      0.520 V      0.520 V                   vds     1.055  V      0.123 V      0.129 V      0.520 V      0.520 V                   vth     0.388  V      0.509 V      0.509 V      0.388 V      0.388 V                   vdsat   0.542  V      0.082 V      0.081 V      0.146 V      0.146 V

As seen given our cascode bias and sizing, we attain equal Vds for both source (m1) and mirror transistors (m2) and hence both branches are matched in performance.

DC Analysis (Sweep)
For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)



Monte Carlo Analysis
In our Montecarlo analysis, we are measuring the effect of transistors’ random mismatch on the output current of our mirror (i.e. how small random variations in individual transistor parameters when added together can result in an overall output current error).

Further details concerning Montecarlo simulation settings have been described under the NMOS resistor-biased cascoded current mirror article and also apply here.



= Results = As compared to the canonical resistor-biased cascoded mirror, the use of a thin-diode to bias our cascode allows us to make do without any resistors and hence minimize area. However, the use of a thin-diode in place of a resistor-bias does come at the expense of an additional current branch and also a larger variation of the cascode bias over PVT and montecarlo. Hence in summary, with a diode-biased cascoded current mirror typically you can attain lower area at the cost of performance and larger a current consumption (although it really depends on the specific application).

For many low-supply/headroom applications, the diode-biased topology can be a good choice to attain reduced area -- where a bias resistor may otherwise prove too large.

For the cascoded current mirror, we can make the following observations


 * The absolute minimum voltage needed for the mirror output branch to be in the sat region is the vdsat of both mirror and cascode devices: vmin_abs = 0.146 + 0.081 >> 0.227


 * However as shown with the current sizing, the mirror requires at least ~0.5 load voltage to yield its maximum Rout. (seen from the plot above where the slope is linear).


 * Error Measurement: We see a variation of 49.92uA to 49.98uA over a linear operating range of 0.5 to 1.3V. This is equivalent to an error of 66.1nA or 0.132% relative to our reference. (keep in mind this is only for the typical corner, the real performance variation should be assessed over PVT where the cascode bias variation can be measured).

Figures of Merit
Output Resistance Rout: 18.911MΩ (measured from 0.5 to 1.3V linear range).

Compliance Voltage Vmin: ~0.5V (from ground)

= References =


 * Designing Analog Chips (Hans Camenzind)
 * Chapter 3 (pages 3-8)


 * Project files.

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.