NMOS source degenerated current mirror

= Schematic Diagram =



= SPICE Simulations =

Walking through our simulation results we have:

Operating Point Analysis
Nominally with matched output load voltage (matched Vds across output transistor), calculating the operating point DC voltages and currents for our mirror.

Relevant source code lines:

OP                      print all * Output current over constant input current (with matched vds load): should be 1 for best match. print (v2#branch/v1#branch)

Operating point DC measurement results (re-formatted for display and analysis):

n1 = 0.8226 V n2 = 0.8226 V n3 = 0.14997 V n4 = 0.14997 V n_pos = 1.30 V v1#branch = -50.0 uA v2#branch = -49.983 uA (v2#branch/v1#branch) = 0.99966

And our relevant transistors' device parameters at the DC OP (re-formatted for display and analysis):

device           m2            m1  model          nmos          nmos gm    340.72 uS     340.72 uS   gmbs     93.793 uS     93.793 uS    rds     971.53 kR     971.53 kR     id     49.987 uA     49.987 uA    vgs     0.67262 V     0.67262 V    vds     0.67262 V     0.67262 V    vbs    -0.14997 V    -0.14997 V    vth     0.42592 V     0.42592 V  vdsat     0.23153 V     0.23153 V

DC Analysis (Sweep)
For measuring the variation of the mirrored output current under different applied loads. We apply a DC sweep to V2 (our load voltage) from 0 to 1.3V in 0.05V increments.

We are plotting the output current magnitude vs drain voltage. (our load voltage at n2)

Relevant source code lines: DC V2 0V 1.3V 0.05V         ; Sweep Drain voltage from 0v to 1.3v in 0.05v increments. ... gnuplot $filename (v2#branch*-1e+06) ylimit $ylow $yhigh xlimit $xlow $xhigh xdelta $xdel title $title xlabel $xlabel ylabel $ylabel

As before our current matching has degraded given finite Rout of the output transistor but to a much lesser extent.



= Results =

For the Simple MOS Current Mirror from our reference, now with the addition of source degeneration we can make the following observations:


 * The absolute minimum voltage needed for the mirror to be in the saturation region is it's Vdsat (roughly a Veff) plus the drop accross the source resistor at the nominal 50uA mirror current i.e:


 * Vmin_abs = 0.23153 + 0.14997 > 0.3815 V


 * However in practice the current mirror requires at least a 0.45V load voltage to be operational with its maximum Rout (this can be seen from the plot above where the slope is linear).


 * Error Measurement: Variation of 49.6uA to 50.159uA over a linear operating range of 0.45 to 1.3V. This is equivalent to an error of 0.559uA or 1.118% relative to our current reference.


 * Note that this topology is symmetrical and can be inverted by using PMOS transistors connected to the positive supply rail instead. (in this case however due to lower holes mobility at large channel lengths, PMOS device widths need to be sized much larger to attain the same Veff)

Figures of Merit
Output Resistance Rout: 1.5206MΩ (measured from 0.45 to 1.3V linear range).

Compliance Voltage Vmin: 0.45V (from ground)

= References =


 * Project files.

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.