PMOS resistor-biased cascoded current mirrors

= Schematic Diagram =



= SPICE Simulations =

Operating Point Analysis
Operating point DC measurement results (re-formatted for display):

n1 = 7.730172e-01 n2 = 6.500000e-01 n3 = 2.730172e-01 n4 = 7.710291e-01 v1#branch = -5.00000e-05 v2#branch = -5.00022e-05 vp = 1.300000e+00 (v2#branch/v1#branch) = 1.000044e+00

And our relevant transistors' device parameters at the DC OP (re-formatted for display): device      m3                    m2                    m1 model        pmos                  pmos                  pmos gm          0.000767124           0.000445368           0.000445348 gmbs        0.000137596           0.000102353           0.000102348 gds         8.2185e-05            1.11588e-06           1.12056e-06 id          5.00022e-05           5.00022e-05           5e-05 vgs         0.498012              0.526983              0.526983 vds         0.121029              0.528971              0.526983 vbs         -0.528971             1.02318e-12           1.01963e-12 vth         0.439805              0.337024              0.337024 vdsat       0.110962              0.198072              0.198072

As seen given our equal Vds for both source and mirror transistors, both branches are very well matched in performance.

DC Analysis (Sweep)
= Results =

Figures of Merit
= References =


 * Designing Analog Chips (Hans Camenzind)


 * Chapter 3 (pages 3-7)


 * Project files.

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.