NMOS characterization (PTM 130)

The characterization testbench schematic for a nominal NMOS transistor in technology is displayed below:

= Schematic diagram = General transistor characterization testbench.



= SPICE simulations =

Description and insights for each of the simulation analyses below will be further expanded in the result section afterwards.

DC analysis (sweep): Large signal parameters
We will be plotting the normalized transistor large-signal I/V transfer curves.

Id vs Vds for different Vgs bias
Here we are sweeping Vds from 0 to 1.3V in 0.05 increments, and subsequently incrementing Vgs from 0.1 to 1.3 in 0.1 increments.

For the I/V characterization curves, a minimum transistor length of L=130nm was used together with a total width of 10um (Wf=1um, Nf=1, m=1).



A couple of helpful insights can be provided given our DC transfer curves above:

The Vdsat delimits the operating region of this transistor. For Vds < Vdsat the device is in the triode region of operation, for Vds > Vdsat the device is in the active (saturation) region of operation.

The maximum current density is attained in deep saturation (maximum Vds) and strong inversion (maximum Vgs). For our NMOS device approaches the traditional "rule of thumb" max figure of 1mA/μm; this is a helpful sanity check.

Keep in mind as well, if we want to bias the device in a different operating region (e.g. weak inversion), these DC transfer curves are useful to understand the maximum attainable current density under those bias conditions; and hence the minimum device width required for the desired bias current.

In designing an amplifier where a large output swing is expected at the output, we often want to set the Vds bias voltage at the mid-point between our supply and the min vdsat for the desired gate-source bias voltage and operating region: this will help us yield the largest swing while maintaining the transistor in saturation.

If we instead are looking into the design of switches, we can make use of these transfer curves to get a good idea for the Ron (ON resistance) we can expect for the transistor device in triode over a range of vds voltages across; recall triode devices experience non-linear resistance. (e.g. take a 1um device, the minimum Ron given a 1.3V gate drive is roughly 0.4v/(0.8ma/μm)*1μm) at the edge of sat to 0.1V/(0.3mA) in deep triode; or loosely 500 to 300 Ω).

Although note in the design of switches we should also understand the parasitics which would set not-only the RC corner frequency/bandwidth of the switch but also the gate-drive requirements. (i.e. if we opt for a very wide switch with low Ron we pay a price in bandwidth and drive power)

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The following are the simulated Vdsat values for each Vgs curve for reference:

Vgs: At Vgs: 0.1 V, Vdsat(@Vds=Vdd): 0.0390523 Vgs: At Vgs: 0.2 V, Vdsat(@Vds=Vdd): 0.0429505 Vgs: At Vgs: 0.3 V, Vdsat(@Vds=Vdd): 0.0604041 Vgs: At Vgs: 0.4 V, Vdsat(@Vds=Vdd): 0.0947588 Vgs: At Vgs: 0.5 V, Vdsat(@Vds=Vdd): 0.134929 Vgs: At Vgs: 0.6 V, Vdsat(@Vds=Vdd): 0.174607 Vgs: At Vgs: 0.7 V, Vdsat(@Vds=Vdd): 0.213001 Vgs: At Vgs: 0.8 V, Vdsat(@Vds=Vdd): 0.250484 Vgs: At Vgs: 0.9 V, Vdsat(@Vds=Vdd): 0.287404 Vgs: At Vgs: 1 V, Vdsat(@Vds=Vdd): 0.323967 Vgs: At Vgs: 1.1 V, Vdsat(@Vds=Vdd): 0.360294 Vgs: At Vgs: 1.2 V, Vdsat(@Vds=Vdd): 0.396457 Vgs: At Vgs: 1.3 V, Vdsat(@Vds=Vdd): 0.4325

Id vs Vgs for different Vbs (back-gate) bias


At Vbs: 0 V, Vth(@Vgs=Vdd): 0.300577 At Vbs: -0.1 V, Vth(@Vgs=Vdd): 0.326095 At Vbs: -0.2 V, Vth(@Vgs=Vdd): 0.350393 At Vbs: -0.3 V, Vth(@Vgs=Vdd): 0.373635 At Vbs: -0.4 V, Vth(@Vgs=Vdd): 0.395952 At Vbs: -0.5 V, Vth(@Vgs=Vdd): 0.41745 At Vbs: -0.6 V, Vth(@Vgs=Vdd): 0.438215 At Vbs: -0.7 V, Vth(@Vgs=Vdd): 0.458321 At Vbs: -0.8 V, Vth(@Vgs=Vdd): 0.477828 At Vbs: -0.9 V, Vth(@Vgs=Vdd): 0.496789 At Vbs: -1 V, Vth(@Vgs=Vdd): 0.51525 At Vbs: -1.1 V, Vth(@Vgs=Vdd): 0.533249 At Vbs: -1.2 V, Vth(@Vgs=Vdd): 0.550821 At Vbs: -1.3 V, Vth(@Vgs=Vdd): 0.567996

DC analysis (sweep): Design parameters vs. Veff (for various Vbs)
Nominal design parameters are plotted below for the reference minimum-length transistor with various back-gate Vbs.

Most important are the design parameter plots for Vbs=0V (i.e. with no back-gate voltage): These plots are most useful for starting choosing a Veff bias point to start a design.



DC analysis (sweep): Design parameters vs. Veff (for various lengths)
Design parameters are plotted below for a set of transistors with lengths spanning from 130nm to 3um (roughly following technology nodes progression) to help compare trade-offs in choosing device dimensions (width chosen as before).



= References =


 * T. Chan Carusone, D. Johns, and K. Martin, Analog Integrated Circuit Design. 2nd edition, J. Wiley & Sons, 2011.


 * P. G. A. Jespers and B. Murmann, Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables. Cambridge: Cambridge University Press, 2017.

= Toolchain =


 * ICclopedia Toolchain.


 * PTM 130nm CMOS SPICE models.